DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-6 & 8 in the reply filed on 01/09/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim process steps must be shown or the feature(s) canceled from the claims:
Claim 1:
a stacked wafer forming step of forming a stacked wafer by stacking a plurality of memory wafers in a bump-less manner;
a dicing step of dicing the stacked wafer into the stacked memories as individual pieces;
a rearrangement step of rearranging a plurality of the stacked memories in a predetermined shape;
a molding step of molding the stacked memories that have been rearranged;
a wiring forming step of forming external wiring on the stacked memories; and
a separation step of separating a resultant semifinished product into memory modules each including a predetermined number of the stacked memories that have been molded.
Claim 2:
after the rearrangement step and before the molding step, an external through electrode forming step of forming an external through electrode that extends in a stacking direction of the stacked memories, wherein
in the rearrangement step, the stacked memories as the individual pieces are disposed on each other and rearranged in a predetermined shape, and
in the molding step, the stacked memories that have been rearranged and the external through electrode are molded.
Claim 8:
wherein in the rearrangement step, the logic chip is stacked on a control chip that is exposed on one surface of the stacked wafer in a stacking direction and that controls the operation of the stacked memories.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “wherein in the rearrangement step, the logic chip is stacked on a control chip that is exposed on one surface of the stacked wafer in a stacking direction”. It is unclear what particular component in the drawings refer to the control chip that is exposed on one surface of the stacked wafer. The Examiner suggests that applicant identifies said feature with a reference numeral in a specific drawing. Correction/clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Chen et al. (US Pub. 2022/0130813A1).
Regarding claim 1, Chen teaches a method for manufacturing a module including a predetermined number of stacked memories, the method comprising:
a stacked wafer forming step of forming a stacked wafer by stacking a plurality of memory wafers in a bump-less manner (see Fig. 1A-1C);
a dicing step of dicing the stacked wafer into the stacked memories as individual pieces (it is understood that a dicing step was performed to obtain individual pieces 30a & 30b that can function as memory chips, see Fig. 1A-1C or see Fig. 1D-1E, wherein stacked memories 20 are diced into individual pieces 20);
a rearrangement step of rearranging a plurality of the stacked memories in a predetermined shape (see Fig. 1E-1H);
a molding step of molding the stacked memories that have been rearranged (Fig. 1I);
a wiring forming step of forming external wiring 12 on the stacked memories (Fig. 1J); and
a separation step of separating a resultant semifinished product into memory modules each including a predetermined number of the stacked memories that have been molded (see Fig. 1K).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and in further view of Zhai et al. (US Patent, 9,659,907).
Regarding claim 2, while Chen teaches the method according to claim 1, further comprising: an external through electrode forming step of forming an external through electrode 23 that extends in a stacking direction of the stacked memories (see Fig. 1D-1E & 1K), wherein in the rearrangement step, the stacked memories as the individual pieces are disposed on each other and rearranged in a predetermined shape (Fig. 1E-1H), and in the molding step, the stacked memories that have been rearranged and the external through electrode are molded (Fig. 1K); However, Chen is silent on wherein the step of forming external electrodes is carried out after the rearrangement step and before the molding step. Nonetheless, Zhai teaches in Fig. 8- Fig. 9, wherein the step of forming external electrodes 140 is carried out after a rearrangement step and before a molding step. This has the advantages of performing an alternative approach. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chen with the sequence of electrode and molding process steps, as taught by Zhai, so as to employ an alternative approach to obtaining a packaging device.
Claims 3-6 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and in further view of Chuang et al. (US Pub. 2021/0202354).
Regarding claim 3, Chen is silent on the method according to claim 1, wherein in the rearrangement step, the stacked memories and a logic chip are rearranged in a predetermined shape, and in the molding step, the stacked memories and the logic chip are molded. However, Chuang teaches in Fig. 12 or Fig. 13, wherein in an rearrangement step, stacked memories (410, 310, 210 & 110) and a logic chip 510 are rearranged in a predetermined shape, and in a molding step (note molding layer 530), the stacked memories 410, 310, 210 & 110) and the logic chip 510 are molded. This has the advantages of providing a logic chip in the stacked structure to process data and execute instructions. Together, the memory chips store short or long term data while the logic chips manage the operation of the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Chen with the logic and memory chips, as taught by Chuang, so as to enhance the operations of the semiconductor device.
Regarding claim 4, the combination of Chen and Chuang teaches the method according to claim 3, wherein in the rearrangement step, the logic chip 510 is stacked on the plurality of stacked memories (Chuang’s Fig. 12 or Fig. 13).
Regarding claim 5, the combination of Chen and Chuang teaches the method according to claim 4, wherein in the rearrangement step, the logic chip 510 is stacked on the plurality of stacked memories (410, 310, 210 & 110) so as to straddle the plurality of stacked memories (Chuang’s Fig. 12 or Fig. 13).
Regarding claim 6, the combination of Chen and Chuang teaches the method according to claim 3, wherein in the rearrangement step, the stacked memories (410, 310, 210 & 110) are stacked on the logic chip 510 (Chuang’s Fig. 12 or Fig. 13 and respective text: rearranging for logic die to be stacked on the memory dies or vice versa would have been within the ordinary skill in the art in view of Chuang).
Regarding claim 8, as best understood, the combination of Chen and Chuang teaches the method according to any one of claim 3, wherein in the rearrangement step, the logic chip 510 is stacked on a control chip (e.g. 410 in Chuang’s Fig. 13 or one of the chips in 20a in Chen’s Fig. 1K can function as a control chip) that is exposed on one surface of the stacked wafer in a stacking direction and that controls the operation of the stacked memories.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818