Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action, in response to the amendment filed 3/5/2026, is a final office action.
Response to Amendment and Arguments
2. Independent claim 1 is amended to include subject matter from previous claims 1, 3, 4 and 7. Previous claim 3 depended on claim 1, previous claim 4 depended on claim 3 and previous claim 7 depended on claim 1. Therefore, amended claim 1 is a new claim that has not been previously examined since claims 3+4 and 7 were individually depended on claim 1. Independent claim 8 is amended to include new claim limitations. Independent claim 10 is amended to include the subject matter from previous claims 10, 12, 13 and 16. Previous claim 12 was dependent on claim 10, previous claim 13 was dependent on claim 12 and previous claim 16 was dependent on claim 10. Therefore, amended claim 10 is a new claim that has not been examined previously since claims 10, 12, 13 and 16 were not in the same claim branch. Claims 12 + 13 and 16 were individually dependent on claim 10. Therefore, the amendment has necessitated the rejections of the claims stated below. Claims 3, 4, 7, 12, 13, 16, 17 and 19-21 are cancelled.
3. Applicant states Arnaud does not disclose the claimed FF linearization part being configured to perform the FF linearization based on first input signals that are reference signals comprising at least the multiple digital input signals and a second input signal that is the intermediate power amplified output signal on page 16 of the remarks. The examiner disagrees. Figure 4 of Arnaud shows the circuit. The feedforward path is shown. Figure 2 describes a related circuit comprising the feed forward signal path with the same or similar components. Paragraph 0039 discloses dual coupler 19 takes a portion of output signal S1 of the channel amplifier to subtract it from signal E back into phase so to eliminate the signal E component and generate the error signal 16. Paragraph 0043 discloses a path of the first loop 1 processes a reference signal Sref generated here by a second analog to digital converter 108, mixed with the carrier 107 at a second mixer then amplified to be recombined with a sample of the output signal S using a doubler coupler 110 so as to generate an error signal e that will be treated in a phase shifter 113 and amplification stages 112 and 114 to be recombined by means of a coupler 130 in the antenna output of the system with signal S1. Paragraph 0049 discloses the error signal e is, after amplification and being set back in opposition of phase, subtracted from the RF output signal of the entire amplifier. Figure 4 of Arnaud shows the input signal is not a reference signal but the input signal, which is provided to the DPD 203 and the components of the digital to analog converter, amplifier, phase shifter, double coupler, amplification states 112, phase shifter 113 and coupler that are shown in the circuit of figure 2. Therefore, Arnaud disclose these features of the amended claim.
On pages 16-17 of the remarks, applicant states Liu does not disclose features of the amended independent claims. These features are rejected in the rejections of the claims stated below, necessitated by the amendment.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
4. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: the DPD part and the FF part in claim 16.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 6, 8, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Arnaud (US 2017/0141739) in view of Liu (US 2006/0240786) further in view of Laporte et al (US 2015/0049841).
Regarding claims 1 and 10, Arnaud discloses a method or apparatus (Figures 3 and 4) for supporting suppression of distortion caused by a power amplifier, "PA", comprised in a transmitter system configured to perform digital predistortion, "DPD", and feedforward, "FF", linearization on digital input signals in order to condition the signals before transmission in a frequency band by a wireless communication network (Figure 4: present and future input signals Din are provided to DPD 203 and the feed forward path controlled by F. FWD control 204.), the PA being used for power amplification in preparation for the transmission and operative with an instantaneous bandwidth, "IBW"', comprising the frequency band (Abstract: a digital radio frequency amplification system includes main amplification channel and distortion correction means including feed-forward correction circuit and pre-distortion correction circuit to adapt the predistortion and minimize errors at the output of the main amplifier.), the method comprising:
obtaining information identifying one or more intermodulation, "IM", components outside the frequency band but within the IBW, which IM components are caused by said PA (Figure 3: the IM components are shown in spectrum 501. The IM components are outside of the frequency band of the desired signals but within the IBW. Paragraph 0040: the error signal enters a second loop and is amplified by adjustable gain and fixed gain amplification stages, the phase shifted by a phase adjustment device to find itself, at the end of the second loop, amplified and phase shifted with the spectrum in opposite phase with the amplifier output signal at the output coupler so that there is a cancellation of the intermodulation products at the antenna output.); and
selectively processing the identified IM components by (Figure 4: signal processing block provides selective outputs to both the DPD 203 and the feed-forward processing path. Figure 3: switch 142. Paragraphs 0060-0063 discloses the positions of the switch 142 controls the selection and connection of the feedback loop to the return path.):
processing a first portion of the identified IM components as part of the DPD to thereby suppress formation of the first portion of the identified IM components (Figure 4: DPD 203 will distort the input signal to suppress distortion at the output of the main amplifier 104.); and
processing a second portion of the identified IM components as part of the FF linearization by adding reference signals to the FF linearization, which reference signals correspond to the second portion of the identified IM components (Figure 3: reference signals Sref are provided in the feed-forward path. The identified IM components are provided to the phase shifter 113 and gain controller 112 prior to being provided to the amplifier 114. The amplified signal is provided to the output of the main amplifier 104 to remove the IM signals as shown in 507.);
generating one FF reference signal that is a model of the identified IM components (Arnaud: paragraph 0015: the feedforward correction circuit comprising a first correction channel fed by a reference signal and transforming it into a first correction signal. Paragraph 0020: the pure useful signal , the pre-distortion signal and the reference signal are generated within a calculator depending of data input, modelling tables of main amplifier and signals from the feedback loop.); and performing the FF linearization using first input signals that comprise the FF reference signal in addition to the multiple digital input signals, thereby supporting suppression of the identified IM components by filters after the power amplification and prior to the transmission (Arnaud: Figure 3. Paragraph 0048: the reference signal Sref used to be subtracted from the useful signal in the main amplifier output so as to generate the error signal in the second loop, is numerically driven in phase and amplitude to eliminate the useful signal input of the second loop. The subtraction takes place after the main amplifier and prior to transmission. The subtraction will filter out the error signal from the useful signal.);
the method is performed by one or more apparatuses comprising a DPD part, a FF linearization part and a power amplification part (Figure 4: DPD 203, F. FWD control 204 controls the feed forward path. The main amplifier is shown receiving the output of the DPD 203.), wherein the DPD part is configured to perform the DPD on the multiple digital input signals and provide digital intermediate output signals (Figure 4: present and future input signals Din are provided to DPD 203.), respectively, wherein the power amplification part comprises the power amplifier and is configured to operate on the digital intermediate output signals and provide an intermediate power amplified output signal (Figure 4: DPD 203. The main amplifier is shown receiving the output of the DPD 203.), wherein the FF linearization part is configured to perform the FF linearization based on first input signals that are reference signals comprising at least the multiple digital input signals and a second input signal that is the intermediate power amplified output signal (paragraph 0015: the feedforward correction circuit comprising a first correction channel fed by a reference signal and transforming it into a first correction signal. Paragraph 0020: the pure useful signal , the pre-distortion signal and the reference signal are generated within a calculator depending of data input, modelling tables of main amplifier and signals from the feedback loop.), and as output provide a power amplified error signal, wherein the transmitter system is configured to transmit a transmission signal based on the intermediate power amplified output signal with removal of the power amplified error signal (Arnaud: Figure 3. Paragraph 0048: the reference signal Sref used to be subtracted from the useful signal in the main amplifier output so as to generate the error signal in the second loop, is numerically driven in phase and amplitude to eliminate the useful signal input of the second loop. The subtraction takes place after the main amplifier and prior to transmission. The subtraction will filter out the error signal from the useful signal.).
Arnaud does not explicitly recite the reference signal is more than one reference signal. However, any one signal can be labelled as more than one signal. The reference signal of Arnaud can be labelled as multiple reference signals. For example, the reference signal can be labelled as two reference signals that are serial and are each half the length of the reference signal Sref (the first half of Sref followed by the second half of Sref). It would have been obvious for one or ordinary skill in the art before the effective filing date of the claimed invention to label a single signal as multiple signals. The processing would operate in the same manner as shown in figure 3 of Arnaud and would yield the same results. This labelling would not alter the operation of the circuit of figure 3 of Arnaud.
Arnaud discloses input signal Din is input to the processor 202 and the DPD 203 (Figure 4). The DPD will process the signal over the signals bandwidth. Arnaud does not disclose the method processes multiple digital signals relating to different frequency bands and performing the DPD in two parts where the second DPD part a second DPD is performed for each one of the identified IM components over at least the IM component's bandwidth, the second DPD part being arranged to suppress formation of the identified IM components.
Liu discloses a method and system for broadband predistortion linearization as stated in the abstract. Figure 4 discloses the system comprises a nonlinear correction device with memory effects 320 comprising an in-band signal predistortion processing unit 306A and an out-of-band signal processing unit 306B. These units will process multiple signals relating to different frequency bands. The in-band signal predistortion processing unit 306A is performed for each one of the input signals over at least the signal’s operative bandwidth. The out-of-band signal predistortion processing unit 306B is performed for each one of the identified IM components over at least the IM component's bandwidth, the second DPD part being arranged to suppress formation of the identified IM components. Paragraph 0047 of Liu discloses in order to compensate the intermodulation in which the upper sideband and the lower sideband are not symmetrical, a conventional way is to use out-of-band compensation. Paragraph 0030 discloses the method and system according to the present invention can compensate the non-linearity with memory effects of the amplifier, and more particularly, compensate the intermodulation distortion due to the memory effects, in which the upper sideband and the lower sideband are not symmetrical. Comparing to the digital predistortion technique of the prior art, the present invention removes the limitation to the predistortion performance caused by the memory effect radically, improves the linearization performance of the DPD greatly and extends the linearization bandwidth of the DPD. For these reasons, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Liu into the method and system of Arnaud.
The combination of Arnaud and Liu does not disclose wherein the second DPD is performed as second separate DPDs, "S-DPDs", targeting the identified IM components, respectively, each second S-DPD performing predistortion over its targeted IM component's bandwidth and wherein the first DPD is performed as first separate DPDs, "S-DPDs", targeting the multiple digital input signals, respectively, each first S-DPD performing predistortion over its targeted digital input signal's operative bandwidth.
Laporte discloses the plurality of in-band frequency bands and the plurality of out-of-band frequency bands that comprise multiple signals in figure 1. Paragraph 0015 recites a DPD includes a separate digital predistorter for each intermodulation distortion frequency band of the one or more intermodulation distortion frequency bands. The first set of digital predistorters are configured to process the input signals to provide the predistorted digital input signals, and a second set of digital predistorters are configured to process the input signals to provide the one or more intermodulation distortion compensation signals. Figure 9 shows a first DPD part that will comprise separate DPDs comprising a PD band 1 54-1 and PD band 2 54-2 that will perform predistortion over its targeted operational bandwidth and a second DPD part targeting IM components that will comprise separate DPDs comprising PD IM3 84-1 and PD IM3 84-2. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of using separate DPDs in the first DPD part targeting the multiple digital input signals and using separate DPDs in the second DPD part targeting the identified IM components as taught by Laporte into the method and apparatus of the combination of Arnaud and Liu to overcome the challenges and cost as stated in paragraph 0012 of Laporte and the need as stated in paragraph 0013 of Laporte.
Regarding claims 6 and 15, the combination discloses, wherein the identified one or more IM components comprise one or more of the first order to fifth order IM components (Arnaud: figure 3. The intermodulation diction is shown in spectrum 501 and 503 and is shown as removed from spectrum 507. This intermodulation component comprises one or more of the first order to fifth order intermodulation components. Liu: Paragraph 0030 discloses the method and system according to the present invention can compensate the non-linearity with memory effects of the amplifier, and more particularly, compensate the intermodulation distortion due to the memory effects, in which the upper sideband and the lower sideband are not symmetrical. Comparing to the digital predistortion technique of the prior art, the present invention removes the limitation to the predistortion performance caused by the memory effect radically, improves the linearization performance of the DPD greatly and extends the linearization bandwidth of the DPD.).
Regarding claim 8, Arnaud discloses a method or apparatus (Figures 3 and 4) for supporting suppression of distortion caused by a power amplifier, "PA", comprised in a transmitter system configured to perform digital predistortion, "DPD", and feedforward, "FF", linearization on digital input signals in order to condition the signals before transmission in a frequency band by a wireless communication network (Figure 4: present and future input signals Din are provided to DPD 203. The feed forward path is controlled by F. FWD control 204.), the PA being used for power amplification in preparation for the transmission and operative with an instantaneous bandwidth, "IBW"', comprising frequency band (Abstract: a digital radio frequency amplification system includes main amplification channel and distortion correction means including feed-forward correction circuit and pre-distortion correction circuit to adapt the predistortion and minimize errors at the output of the main amplifier.), the method comprising:
obtaining information identifying one or more intermodulation, "IM", components outside the frequency band but within the IBW, which IM components are caused by said PA (Figure 3: the IM components are shown in spectrum 501. The IM components are outside of the frequency band of the desired signals but within the IBW. Paragraph 0040: the error signal enters a second loop and is amplified by adjustable gain and fixed gain amplification stages, the phase shifted by a phase adjustment device to find itself, at the end of the second loop, amplified and phase shifted with the spectrum in opposite phase with the amplifier output signal at the output coupler so that there is a cancellation of the intermodulation products at the antenna output.); and
selectively processing the identified IM components by (Figure 4: signal processing block provides selective outputs to both the DPD 203 and the feed-forward processing path. Figure 3: switch 142. Paragraphs 0060-0063 discloses the positions of the switch 142 controls the selection and connection of the feedback loop to the return path.):
processing a first portion of the identified IM components as part of the DPD to thereby suppress formation of the first portion of the identified IM components (Figure 4: DPD 203 will distort the input signal to suppress distortion at the output of the main amplifier 104.); and
processing a second portion of the identified IM components as part of the FF linearization by adding reference signals to the FF linearization, which reference signals correspond to the second portion of the identified IM components (Figure 3: reference signals Sref are provided in the feed-forward path. The identified IM components are provided to the phase shifter 113 and gain controller 112 prior to being provided to the amplifier 114. The amplified signal is provided to the output of the main amplifier 104 to remove the IM signals as shown in 507.).
generating one FF reference signal that is a model of the identified IM components (Arnaud: paragraph 0015: the feedforward correction circuit comprising a first correction channel fed by a reference signal and transforming it into a first correction signal. Paragraph 0020: the pure useful signal , the pre-distortion signal and the reference signal are generated within a calculator depending of data input, modelling tables of main amplifier and signals from the feedback loop.); and performing the FF linearization using first input signals that comprise the FF reference signal in addition to the multiple digital input signals, thereby supporting suppression of the identified IM components by filters after the power amplification and prior to the transmission (Arnaud: Figure 3. Paragraph 0048: the reference signal Sref used to be subtracted from the useful signal in the main amplifier output so as to generate the error signal in the second loop, is numerically driven in phase and amplitude to eliminate the useful signal input of the second loop. The subtraction takes place after the main amplifier and prior to transmission. The subtraction will filter out the error signal from the useful signal.).
the method is performed by one or more apparatuses comprising a DPD part, a FF linearization part and a power amplification part (Figure 4: DPD 203, F. FWD control 204 controls the feed forward path. The main amplifier is shown receiving the output of the DPD 203.), wherein the DPD part is configured to perform the DPD on the multiple digital input signals and provide digital intermediate output signals (Figure 4: present and future input signals Din are provided to DPD 203.), respectively, wherein the power amplification part comprises the power amplifier and is configured to operate on the digital intermediate output signals and provide an intermediate power amplified output signal (Figure 4: DPD 203. The main amplifier is shown receiving the output of the DPD 203.), wherein the FF linearization part is configured to perform the FF linearization based on first input signals that are reference signals comprising at least the multiple digital input signals and a second input signal that is the intermediate power amplified output signal (paragraph 0015: the feedforward correction circuit comprising a first correction channel fed by a reference signal and transforming it into a first correction signal. Paragraph 0020: the pure useful signal , the pre-distortion signal and the reference signal are generated within a calculator depending of data input, modelling tables of main amplifier and signals from the feedback loop.), and as output provide a power amplified error signal, wherein the transmitter system is configured to transmit a transmission signal based on the intermediate power amplified output signal with removal of the power amplified error signal (Arnaud: Figure 3. Paragraph 0048: the reference signal Sref used to be subtracted from the useful signal in the main amplifier output so as to generate the error signal in the second loop, is numerically driven in phase and amplitude to eliminate the useful signal input of the second loop. The subtraction takes place after the main amplifier and prior to transmission. The subtraction will filter out the error signal from the useful signal.).
Arnaud does not explicitly recite the reference signal is more than one reference signal. However, any one signal can be labelled as more than one signal. The reference signal of Arnaud can be labelled as multiple reference signals. For example, the reference signal can be labelled as two reference signals that are serial and are each half the length of the reference signal Sref (the first half of Sref followed by the second half of Sref). It would have been obvious for one or ordinary skill in the art before the effective filing date of the claimed invention to label a single signal as multiple signals. The processing would operate in the same manner as shown in figure 3 of Arnaud and would yield the same results. This labelling would not alter the operation of the circuit of figure 3 of Arnaud.
Though Arnaud does not explicitly show a computer readable storage medium storing a computer program comprising instructions that when executed cause one or more apparatuses to perform the method stated above, Arnaud discloses other processes can be added to the digital signal by software in the calculator as shown in paragraph 0083. Arnaud discloses using software to be executed by a processor to cause a device to perform a method. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teaching of Arnaud to utilize software to perform a method to perform the method taught by Arnaud. The use of software can minimize the size and complexity of the hardware associated with the method. This will reduce the cost and improve the effectiveness and efficiency of the method.
Arnaud discloses input signal Din is input to the processor 202 and the DPD 203 (Figure 4). The DPD will process the signal over the signals bandwidth. Arnaud does not disclose the method processes multiple digital signals relating to different frequency bands and performing the DPD in two parts where the second DPD part a second DPD is performed for each one of the identified IM components over at least the IM component's bandwidth, the second DPD part being arranged to suppress formation of the identified IM components.
Liu discloses a method and system for broadband predistortion linearization as stated in the abstract. Figure 4 discloses the system comprises a nonlinear correction device with memory effects 320 comprising an in-band signal predistortion processing unit 306A and an out-of-band signal processing unit 306B. These units will process multiple signals relating to different frequency bands. The in-band signal predistortion processing unit 306A is performed for each one of the input signals over at least the signal’s operative bandwidth. The out-of-band signal predistortion processing unit 306B is performed for each one of the identified IM components over at least the IM component's bandwidth, the second DPD part being arranged to suppress formation of the identified IM components. Paragraph 0047 of Liu discloses in order to compensate the intermodulation in which the upper sideband and the lower sideband are not symmetrical, a conventional way is to use out-of-band compensation. Paragraph 0030 discloses the method and system according to the present invention can compensate the non-linearity with memory effects of the amplifier, and more particularly, compensate the intermodulation distortion due to the memory effects, in which the upper sideband and the lower sideband are not symmetrical. Comparing to the digital predistortion technique of the prior art, the present invention removes the limitation to the predistortion performance caused by the memory effect radically, improves the linearization performance of the DPD greatly and extends the linearization bandwidth of the DPD. For these reasons, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Liu into the method and system of Arnaud.
The combination of Arnaud and Liu does not disclose wherein the second DPD is performed as second separate DPDs, "S-DPDs", targeting the identified IM components, respectively, each second S-DPD performing predistortion over its targeted IM component's bandwidth and wherein the first DPD is performed as first separate DPDs, "S-DPDs", targeting the multiple digital input signals, respectively, each first S-DPD performing predistortion over its targeted digital input signal's operative bandwidth.
Laporte discloses the plurality of in-band frequency bands and the plurality of out-of-band frequency bands that comprise multiple signals in figure 1. Paragraph 0015 recites a DPD includes a separate digital predistorter for each intermodulation distortion frequency band of the one or more intermodulation distortion frequency bands. The first set of digital predistorters are configured to process the input signals to provide the predistorted digital input signals, and a second set of digital predistorters are configured to process the input signals to provide the one or more intermodulation distortion compensation signals. Figure 9 shows a first DPD part that will comprise separate DPDs comprising a PD band 1 54-1 and PD band 2 54-2 that will perform predistortion over its targeted operational bandwidth and a second DPD part targeting IM components that will comprise separate DPDs comprising PD IM3 84-1 and PD IM3 84-2. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of using separate DPDs in the first DPD part targeting the multiple digital input signals and using separate DPDs in the second DPD part targeting the identified IM components as taught by Laporte into the method and apparatus of the combination of Arnaud and Liu to overcome the challenges and cost as stated in paragraph 0012 of Laporte and the need as stated in paragraph 0013 of Laporte.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M. BURD whose telephone number is (571)272-3008. The examiner can normally be reached 9:30 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN M BURD/Primary Examiner, Art Unit 2632 5/18/2026
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