DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 28, 2025, has been entered.
Claims 1-21 are pending in this office action and presented for examination. Claims 2-3, 5-6, 11-14, and 16-17 are newly amended by the response received November 28, 2025.
Examiner notes the following (not necessarily comprehensive) non-compliant specification amendment issues in the response dated November 28, 2025:
Paragraph numbers (starting with paragraph [0012]) have been inserted or amended without appropriate markup.
Marked-up amendments made across paragraphs [0010]-[0029] of the amended specification of the response dated November 28, 2025, were already made in the previous version of the specification.
Paragraph [0032] of the amended specification of the response dated November 28, 2025, includes an underlined “instruction”; however, this language was already present in the previous version of the specification (in paragraph [0017] of the amended specification of the response dated August 8, 2025).
Paragraph [0053] of the amended specification of the response dated November 28, 2025, includes an underlined “instruction”; however, this language was already present in the previous version of the specification (in paragraph [0038] of the amended specification of the response dated August 8, 2025).
Paragraph [0058] of the amended specification of the response dated November 28, 2025, includes an underlined “235”; however, this language was already present in the previous version of the specification (in paragraph [0043] of the amended specification of the response dated August 8, 2025).
Paragraph [0058] of the amended specification of the response dated November 28, 2025, includes a deleted “230”; however, this language was already deleted in the previous version of the specification (in paragraph [0043] of the amended specification of the response dated August 8, 2025).
Paragraph [0058] of the amended specification of the response dated November 28, 2025, includes an underlined “32-bit”; however, this language was already present in the previous version of the specification (in paragraph [0043] of the amended specification of the response dated August 8, 2025).
Paragraph [0058] of the amended specification of the response dated November 28, 2025, includes a deleted “32 bit”; however, this language was already deleted in the previous version of the specification (in paragraph [0043] of the amended specification of the response dated August 8, 2025).
Paragraph [0074], line 5, of the amended specification of the response dated November 28, 2025, includes a deleted “s”; however, this language was already deleted in the previous version of the specification (in paragraph [0059] of the amended specification of the response dated August 8, 2025).
Paragraph [0094], line 5, of the amended specification of the response dated November 28, 2025, deletes “bit” without appropriate strikethrough.
While the examiner has nevertheless sent out an office action rather than a notice of non-compliant amendment for the purposes of compact prosecution, Examiner requests that future amendments be made in the appropriate manner conveyed in MPEP 714 to avoid future notices of non-compliant amendment.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Examiner submits that the general concept of multithreading (and therefore a multithreaded architecture, and processing thread execution code) and the general designer goal of power and latency reduction were widespread before the effective filing date of the claimed invention. Examiner further submits that inserting instruction hints (e.g., compiler hints; for example, note that the definition statement for G06F9/3846 includes “Branch prediction performed by compiler, and not dependent on runtime conditions, e.g. hint bits”) was likewise well-known before the effective filing date of the claimed invention. Therefore, the title is not clearly indicative of the invention to which the claims are directed. Examiner recommends incorporating the subject matter of the last paragraph of claim 1 into the title. Examiner generally notes that if a satisfactory title is not supplied by the applicant, the examiner will, at the time of allowance, change the title by an examiner’s amendment to increase informative value in indexing, classifying, searching, etc.
The disclosure is objected to because of the following informalities. Appropriate correction is required.
Paragraph [0053] of the amended specification received November 28, 2025, discloses “Fig. 2A is an example schematic illustration of a plurality of instruction threads scheduled for consecutive execution, utilized to describe an embodiment. In an embodiment, a plurality of instruction threads 210-1 through 210-N are processed consecutively (i.e., serially, in a non-pipelined manner), such that a first instruction thread 210-1 is completely processed before processing a second instruction thread 210-2”. Paragraph [0032] of the amended specification received November 28, 2025, discloses “Figure 2A is an example schematic illustration of a plurality of instruction threads scheduled for consecutive execution, utilized to describe an embodiment”. However, Figure 2A, as well as other portions of the specification such as paragraph [0054] of the amended specification received November 28, 2025, refers to the elements associated with these reference characters as instructions rather than instruction threads. Therefore, the specification does not clearly set forth the invention.
Drawings
The drawings are objected to because:
On drawing sheet 3 of 8, the spelling of “FGURE 2B” should be fixed.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-4 and 13-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites the limitation “The method of claim 1, further comprising: generating an instruction to add a number to a hardcoded register, wherein the number indicates a number of the plurality of subsequent independent instructions” in lines 1-3. Claim 1, upon which claim 2 is dependent, recites the limitation “inserting into an instruction an instruction hint which when read by an instruction scheduler configures the instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions” in lines 7-9. However, the original disclosure does not appear to provide support for claim 2 in the context of claim 1. For example, the original disclosure (e.g., paragraph [0026]) does not appear to provide support for two different instructions (i.e., “an instruction” of claim 1, line 7, and “an instruction” of claim 2, line 2) associated with the recited functionality being associated, in the manner recited, with the same plurality of subsequent independent instructions.
Claims 3-4 are rejected for failing to alleviate the rejection of claim 2 above.
Claim 13 recites the limitation “The system of claim 12, wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate an instruction to add a number to a hardcoded register, wherein the number indicates a number of the plurality of subsequent independent instructions” in lines 1-5. Claim 12, upon which claim 13 is dependent, recites the limitation “insert into an instruction an instruction hint which when read by an instruction scheduler configures the instruction scheduler of the processing circuitry to serially execute the plurality of subsequent independent instructions” in lines 10-12. However, the original disclosure does not appear to provide support for the amended limitation of claim 13 in the context of claim 12. For example, the original disclosure (e.g., paragraph [0026]) does not appear to provide support for two different instructions (i.e., “an instruction” of claim 12, line 10, and “an instruction” of claim 13, line 4) associated with the recited functionality being associated, in the manner recited, with the same plurality of the subsequent independent instructions.
Claims 14-15 are rejected for failing to alleviate the rejection of claim 13 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the instruction scheduler of the processing circuitry” in line 8. However, there is insufficient antecedent basis for this limitation in the claim.
Claims 2-10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 5 recites the limitation “the number of subsequent instructions of the second thread” in line 4. However, there is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the instruction scheduler of the processing circuitry” in line 11. However, there is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “the instruction scheduler of the processing circuitry” in line 11. However, there is insufficient antecedent basis for this limitation in the claim.
Claims 13-21 are rejected for failing to alleviate the rejection of claim 12 above.
Claim 16 recites the limitation “the number of subsequent instructions of the second thread” in line 6. However, there is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-12, and 16-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Wang) (US 20150220346 A1).
Consider claim 1, Wang discloses a method for power and latency reduction ([0035], lines 3-4, minimizes unused clock cycles; [0008], lines 3-4, very little power consumption) in processing thread execution code ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) in a multithreaded architecture ([0035], line 4, multithreaded processor), comprising: receiving a plurality of threads, each thread including a plurality of instructions for execution ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) on a core of a plurality of cores of a processing circuitry ([0036], lines 6-7, the multithreaded processor 100 may comprise a plurality of hardware thread units 102a-102n); detecting in a first thread of the plurality of threads ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) a plurality of subsequent independent instructions ([0038], lines 3-6, the instruction validity prediction logic 118 may be configured to determine if any dependencies exits between instructions ready to be issued in an issuing sequence during a clock cycle; [0043], line 4, independent instructions; [0043], lines 9-10, any number of bits may be chained together based on the capabilities of a particular processor); and inserting into an instruction an instruction hint ([0038], lines 6-11, the dependency information provided by the instruction validity prediction logic 118 may be encoded and output in the form of "chaining bits" used to determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) which when read by an instruction scheduler ([0036], lines 11-12, instruction issue controller) configures the instruction scheduler of the processing circuitry ([0036], lines 11-12, instruction issue controller) to serially execute the plurality of subsequent independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 5, Wang discloses the method of claim 1 (see above), further comprising: detecting in a second thread of the plurality of threads ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) a value of a bit indicator, wherein the bit indicator indicates a number of subsequent instructions; and serially executing the number of subsequent instructions of the second thread ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 6, Wang discloses the method of claim 1 (see above), further comprising: executing an instruction of a second thread of the plurality of threads, in response to completing execution of the plurality of subsequent independent instructions of the first thread of the plurality of threads ([0038], lines 11-17, in an example, if the next hardware thread unit (e.g., 102a) has no valid executable instructions in next cycle but the current hardware thread unit (e.g., 102b) has instructions waiting that may issue, then the logic of the instruction validity prediction logic 118 may permit the current hardware thread to issue an instruction in the next clock cycle).
Consider claim 7, Wang discloses the method of claim 1 (see above), further comprising: executing a first instruction of the plurality of subsequent independent instructions at a first clock cycle; and executing a second instruction of the plurality of subsequent independent instructions at a second clock cycle, wherein the first clock cycle immediately precedes the second clock cycle ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 8, Wang discloses the method of claim 1 (see above), further comprising: generating the instruction hint to include a predetermined bit set to a value indicating that a next instruction is an independent instruction ([0036], lines 11-12, instruction issue controller) to serially execute the plurality of subsequent independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 9, Wang disclose the method of claim 8 (see above), further comprising: detecting that the instruction is of a first category; and setting a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 10, Wang discloses the method of claim 9 (see above), further comprising: executing the next independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 11, Wang discloses a non-transitory computer-readable medium ([0036], line 14, memory) storing a set of instructions ([0076], lines 4-10, the method 700 may be performed, for example, by chaining bit encoder 605 of the computer processor of FIGS. 1 and 6, or by other types of computer processors and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0092], lines 4-9, the method 900 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0098], lines 4-9, the method 1000 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof) for power and latency reduction ([0035], lines 3-4, minimizes unused clock cycles; [0008], lines 3-4, very little power consumption) in processing thread execution code ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) in a multithreaded architecture ([0035], line 4, multithreaded processor), the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device ([0076], lines 4-10, the method 700 may be performed, for example, by chaining bit encoder 605 of the computer processor of FIGS. 1 and 6, or by other types of computer processors and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0092], lines 4-9, the method 900 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0098], lines 4-9, the method 1000 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof) to: receive a plurality of threads, each thread including a plurality of instructions for execution ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) on a core of a plurality of cores of a processing circuitry ([0036], lines 6-7, the multithreaded processor 100 may comprise a plurality of hardware thread units 102a-102n); detect in a first thread of the plurality of threads ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) a plurality of subsequent independent instructions ([0038], lines 3-6, the instruction validity prediction logic 118 may be configured to determine if any dependencies exits between instructions ready to be issued in an issuing sequence during a clock cycle; [0043], line 4, independent instructions; [0043], lines 9-10, any number of bits may be chained together based on the capabilities of a particular processor); and insert into an instruction an instruction hint ([0038], lines 6-11, the dependency information provided by the instruction validity prediction logic 118 may be encoded and output in the form of "chaining bits" used to determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) which when read by an instruction scheduler ([0036], lines 11-12, instruction issue controller) configures the instruction scheduler of the processing circuitry ([0036], lines 11-12, instruction issue controller) to serially execute the plurality of subsequent independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 12, Wang discloses a system for power and latency reduction ([0035], lines 3-4, minimizes unused clock cycles; [0008], lines 3-4, very little power consumption) in processing thread execution code ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) in a multithreaded architecture ([0035], line 4, multithreaded processor) comprising: a processing circuitry ([0035], line 4, multithreaded processor); and a memory ([0036], line 14, memory), the memory containing instructions that, when executed by the processing circuitry, configured the system ([0076], lines 4-10, the method 700 may be performed, for example, by chaining bit encoder 605 of the computer processor of FIGS. 1 and 6, or by other types of computer processors and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0092], lines 4-9, the method 900 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof; [0098], lines 4-9, the method 1000 may be performed, for example, by the (e.g., multithreaded) computer processor 100 of FIGS. 1 and 6, and may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processing device), or a combination thereof) to: receive a plurality of threads, each thread including a plurality of instructions for execution ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) on a core of a plurality of cores of a processing circuitry ([0036], lines 6-7, the multithreaded processor 100 may comprise a plurality of hardware thread units 102a-102n); detect in a first thread of the plurality of threads ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) a plurality of subsequent independent instructions ([0038], lines 3-6, the instruction validity prediction logic 118 may be configured to determine if any dependencies exits between instructions ready to be issued in an issuing sequence during a clock cycle; [0043], line 4, independent instructions; [0043], lines 9-10, any number of bits may be chained together based on the capabilities of a particular processor); and insert into an instruction an instruction hint ([0038], lines 6-11, the dependency information provided by the instruction validity prediction logic 118 may be encoded and output in the form of "chaining bits" used to determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) which when read by an instruction scheduler ([0036], lines 11-12, instruction issue controller) configures the instruction scheduler of the processing circuitry ([0036], lines 11-12, instruction issue controller) to serially execute the plurality of subsequent independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 16, Wang discloses the system of claim 12 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: detect in a second thread of the plurality of threads ([0038], lines 9-10, determine in advance if a current software thread and any additional software threads have valid instructions that can be issued in the next clock cycle) a value of a bit indicator, wherein the bit indicator indicates a number of subsequent instructions; and serially execute the number of subsequent instructions of the second thread ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 17, Wang discloses the system of claim 12 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: execute an instruction of a second thread of the plurality of threads, in response to completing execution of the plurality of subsequent independent instructions of the first thread of the plurality of threads ([0038], lines 11-17, in an example, if the next hardware thread unit (e.g., 102a) has no valid executable instructions in next cycle but the current hardware thread unit (e.g., 102b) has instructions waiting that may issue, then the logic of the instruction validity prediction logic 118 may permit the current hardware thread to issue an instruction in the next clock cycle).
Consider claim 18, Wang discloses the system of claim 12 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: execute a first instruction of the plurality of subsequent independent instructions at a first clock cycle; and execute a second instruction of the plurality of subsequent independent instructions at a second clock cycle, wherein the first clock cycle immediately precedes the second clock cycle ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 19, Wang discloses the system of claim 12 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate the instruction hint to include a predetermined bit set to a value indicating that a next instruction is an independent instruction ([0036], lines 11-12, instruction issue controller) to serially execute the plurality of subsequent independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 20, Wang disclose the system of claim 19 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: detect that the instruction is of a first category; and set a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Consider claim 21, Wang discloses the system of claim 20 (see above), wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: execute the next independent instructions ([0044], lines 1-12, in an example, for a typical pipelined-processor, if inter-instruction dependencies exist, the pipeline must stall until the dependencies are resolved. If the chaining bit is set to "1", this is an indication that the next instruction has no control or data dependencies with any instructions within the current instruction chain. Hence, the instruction may be issued immediately. If the chaining bit is set to "0", this is an indication that the next instruction has control and/or data dependencies with at least one instruction within the current instruction chain. Hence, the execution of this instruction cannot commence until all instructions in the current chain complete execution and exit the pipeline).
Allowable Subject Matter
Claims 2-4 and 13-15 contain allowable subject matter. However, as explained above, claims 2-4 and 13-15 do not appear to be supported by the original disclosure.
Response to Arguments
Applicant on page 2 argues: ‘The title of the invention stands objected to. Without conceding to the propriety of the objection, Applicant requests the title be changed to "System and Method for Power and Latency Reduction by Inserting Instruction Hints in Processing Thread Execution Code in a Multithreaded Architecture".’
Examiner submits that the general concept of multithreading (and therefore a multithreaded architecture, and processing thread execution code) and the general designer goal of power and latency reduction were widespread before the effective filing date of the claimed invention. Examiner further submits that inserting instruction hints (e.g., compiler hints; for example, note that the definition statement for G06F9/3846 includes “Branch prediction performed by compiler, and not dependent on runtime conditions, e.g. hint bits”) was likewise well-known before the effective filing date of the claimed invention. Therefore, the title is not clearly indicative of the invention to which the claims are directed. Examiner recommends incorporating the subject matter of the last paragraph of claim 1 into the title. Examiner generally notes that if a satisfactory title is not supplied by the applicant, the examiner will, at the time of allowance, change the title by an examiner’s amendment to increase informative value in indexing, classifying, searching, etc.
Applicant on page 2 argues: “Par. [0038] of the Specification has been amended to register the objection to par. [0017] and [0038] moot.”
Examiner first generally notes that the amended specification received November 28, 2025, has different paragraph numbering, such that paragraph [0038] of the amended specification received November 28, 2025, is not amended.
Examiner further notes that paragraph [0053] of the amended specification received November 28, 2025 (which appears to correspond to previous paragraph [0038]) does not appear to be marked up in a compliant manner. For example, [0053] of the amended specification received November 28, 2025, contains an underlined “instruction” in line 1; however, this language was previously present. (Examiner generally notes that the amended specification received November 28, 2025, appears to contain a substantial amount of non-compliant markup — see paragraph 4 above.)
Nevertheless, Examiner notes that paragraph [0053] of the amended specification received November 28, 2025, has been amended in a manner which conflicts with the remainder of the disclosure.
For example, paragraph [0053] of the amended specification received November 28, 2025, discloses “Fig. 2A is an example schematic illustration of a plurality of instruction threads scheduled for consecutive execution, utilized to describe an embodiment. In an embodiment, a plurality of instruction threads 210-1 through 210-N are processed consecutively (i.e., serially, in a non-pipelined manner), such that a first instruction thread 210-1 is completely processed before processing a second instruction thread 210-2”. Paragraph [0032] of the amended specification received November 28, 2025, discloses “Figure 2A is an example schematic illustration of a plurality of instruction threads scheduled for consecutive execution, utilized to describe an embodiment”. However, Figure 2A, as well as other portions of the specification such as paragraph [0054] of the amended specification received November 28, 2025, refers to the elements associated with these reference characters as instructions rather than instruction threads.
Applicant on page 2 argues: “Par. [0044] of the Specification refers to reference character 220-2. Applicants submitted substitute drawings render this objection moot.”
In view of the aforementioned substitute drawings, the associated previously presented objection is withdrawn.
Applicant on page 2 argues: “Please find submitted herewith a clean and amended substitute specification.”
Examiner generally notes that a clean substitute specification does not appear to be included in the response received November 28, 2025. (Examiner also notes that a previous “clean” substitute specification, dated August 8, 2025, was not fully clean; for example, see paragraph [0043] of the aforementioned document, in which amendment markup remains.)
Applicant on page 3 argues: “Replacement drawings are submitted together with arguments which the Office Action did not rebut.”
However, Examiner notes that the aforementioned arguments (dated August 8, 2025) referred to updated and amended Figures, and Examiner had noted in the office action dated August 27, 2025, that the response received August 8, 2025, did not appear to include replacement drawing sheets. Therefore, Examiner could not make a determination regarding whether the updated and amended Figures would overcome the objections. Applicant does not appear to mention or acknowledge the unincluded replacement drawing sheets in the instant arguments.
Applicant on page 3 argues: ‘Specifically, Applicants noted that with respect to the object that the step associated with reference character S410 in Fig. 4 does not "wholly track" to reference S410 of paragraph [0054], Applicants disagree. Initially, "wholly track" does not appear to be a standard adhered to in the MPEP and as such Applicants have no guidance as to how such an objection may be overcome. The step S410 in the Specification cites "a plurality of threads is received", and goes on to say that (emphasis added): "In certain embodiments, a kernel is received as a portion of code, which is executed by multiple threads. Each thread operates on different data, but executes the same code on the different data, according to an embodiment. It is clear that a kernel includes multiple threads, also known as a plurality of threads, which is what the Figure initially showed. Therefore, it would appear that the step in Fig. 4 and S410 in the Specification do wholly track. Regardless, in order to advance prosecution, Fig. 4 has been amended.’
Examiner submits that the MPEP supports the requirement that a step number described in the Figures and that same step number as described in the specification should be consistent with each other. For example, the first sentence of MPEP 608 conveys that a patent application as filed must contain a full “and clear” disclosure of the invention. Examiner submits that “Receive a kernel” and “a plurality of threads is received” is not necessarily consistent and therefore leads to a lack of clarity regarding the invention. For example, Applicant’s citation in the specification does not disclose that a “kernel” and “a plurality of threads” are the same; rather, Applicant’s citation in the specification discloses “a kernel is received as a portion of code, which is executed by multiple threads”. It is unclear as to how a “kernel” and “a plurality of threads” would be the same when the kernel is “executed by” multiple threads.
Examiner further notes that MPEP 608.01(g) conveys that “The reference characters must be properly applied, no single reference character being used for two different parts”.
Nevertheless, in view of Applicant’s amendment to FIG. 4, the associated objection is withdrawn.
Applicant on page 3 argues: ‘The step S430 is also objected to as not "wholly tracking". Fig. 4 has "Insert an instruction hint" while par. [0061] of the Specification cites "At S430, a hint instruction is inserted". While Applicants do not agree that these do not "wholly track", Fig. 4 has been updated to render this objection moot.’
Examiner submits that one of ordinary skill in the art would readily recognize that “an instruction hint” is not necessarily the same as a “hint instruction”. For example, a counter value of “11” to indicate “predict strongly taken” in basic branch prediction may be considered an instruction hint (given that it is a hint on how to process the branch instruction), but that counter value is not an instruction itself. Examiner submits that the instant disclosure would not be clear if it is unclear as to whether the instant invention in general, or a specific step in particular, entails a “hint instruction” or an “instruction hint”.
Nevertheless, in view of Applicant’s amendment to FIG. 4, the associated objection is withdrawn.
Applicant on page 3 argues: “With respect to Fig. 5, Applicants disagreed with the cause for objection, and in order to advance prosecution, Fig. 5 was amended, rendering the objection moot.”
In view of Applicant’s amendment to FIG. 5, the associated objection is withdrawn.
Applicant on page 3 argues: “No response was received to any of Applicants' arguments. Applicants respectfully request once more that any future response which does not include a notice of allowance indicate the standard in the MPEP which the Examiner is referring to, so that Applicants have an opportunity to either argue the merit or file a suitable amendment.”
However, as noted above, the aforementioned arguments (dated August 8, 2025) referred to updated and amended Figures, and Examiner had noted that the response received August 8, 2025, did not appear to include replacement drawing sheets. Therefore, Examiner could not make a determination regarding whether the updated and amended Figures would overcome the objections. Applicant does not appear to mention or acknowledge the unincluded replacement drawing sheets in the instant arguments.
In addition, as noted above, the first sentence of MPEP 608 conveys that a patent application as filed must contain a full “and clear” disclosure of the invention. Examiner submits that a step number described in the Figures and that same step number as described in the specification not being consistent with each other does not reflect a clear disclosure of the invention. Examiner further notes that MPEP 608.01(g) conveys that “The reference characters must be properly applied, no single reference character being used for two different parts”. (Similarly, Examiner submits that reference numbers 210-1 through 210-N being used in some places to refer to different instruction threads, and in other places used to refer to different instructions in a same thread, does not reflect a clear disclosure of the invention.)
Applicant on page 3 argues: ‘Fig. 2A is objected as having reference characters 211, 212, 213, and 214 "mingle" with dashed lines. None of the reference characters intersect with any dashed line. The dashed lines aid in showing clock cycles, and it is clear from the Specification and Figure that the reference characters refer to individual operations of the instruction thread. As there is no mingling, withdrawal of this objection is respectfully solicited.’
Examiner maintains that Figure 2A of the drawings dated March 12, 2025, shows the aforementioned mingling. Nevertheless, in view of the newly amended drawings dated November 28, 2025, which alleviate the aforementioned mingling, the associated drawing objection is withdrawn. (In addition, and with relevance to the above response to arguments regarding the amendments to the specification, Examiner notes that Applicant’s argument above characterizes Figure 2A as showing reference characters that refer to “individual operations of the instruction thread”.)
However, the newly amended drawings dated November 28, 2025, introduce additional objectionable subject matter. For example, in the following figure, “FIGURE 2B” has been changed to “FGURE 2B”.
Applicant across pages 10-11 argues: “This ground of rejection is respectfully avoided. The Specification teaches … (Specification, par [0026]) Claim 2 recites … Support for the claim is practically verbatim in the Specification, and as such, it is entirely unclear to Applicants how the Office Action has interpreted this otherwise. Claim 13 is rejected under similar rationale and accordingly Applicants apply the same arguments, mutatis mutandis, with respect to claim 13. Claims 3-4 and 14-15 depend on claims 2 and 13 respectively, and as such as allowable.”
However, Applicant’s arguments do not appear to address the particular rationale for rejection conveyed in the previous (and current) Office Action. For example, Applicant’s arguments appear to be merely directed toward how claim 2, in a vacuum, is supported, whereas the rationale for rejection conveyed in the previous (and current) Office Action set forth how claim 2, in the specific context of parent claim 1, did not appear to be supported by the original disclosure. For example, Applicant’s arguments do not appear to address the last two sentences of the rejection.
Applicant on page 11 argues: “This ground of rejection is respectfully avoided. Essentially all of these rejections relate to improper introduction or antecedent basis for various elements. Applicants respectfully submit that per MPEP 2173.05(e), the rejection under 112(b) is improper, as (emphasis added): … Applicants contend that the scope of the claims was entirely reasonably ascertainable by those skilled in the art, and in fact, the Office Action has not shown otherwise. Regardless, the claim amendments render this rejection moot. Withdrawal of these rejections is respectfully requested.”
Examiner notes that Applicant has not provided specific arguments with respect to why, despite failure to provide explicit antecedent basis, the relevant claim limitations would nevertheless be reasonably ascertainable by those skilled in the art. Nevertheless, in view of the aforementioned claim amendments, associated previously presented rejections are withdrawn.
Applicant across pages 11-12 argues: “Initially, Applicants strongly protest as the Office Action is improperly made final. This grounds of rejection should have been made in the prior Office Action dated May 8, 2025. Per MPEP 707.07(g), piecemeal examination should be avoided, and here this is precisely what the instant Office Action does. The Office Action further does not adhere to the standards laid out in MPEP 2173.06 covering Compact Prosecution, which state that (emphasis added): The goal of examination is to clearly articulate any rejection early in the prosecution process so that the applicant has the chance to provide evidence of patentability and otherwise reply completely at the earliest opportunity. See MPEP § 706. Under the principles of compact prosecution, the examiner should review each claim for compliance with every statutory requirement for patentability in the initial review of the application and identify all of the applicable grounds of rejection in the first Office action to avoid unnecessary delays in the prosecution of the application. The Office Action has clearly failed to do so, and has now made the current action improperly final.”
Examiner first notes that a rejection under 35 USC 102 using Wang was not made in the Office Action dated May 8, 2025, because Examiner did not believe Wang taught the unamended claim language. Nevertheless, Examiner will take into consideration Applicant’s apparent argument that Wang may be as applicable to the unamended claims as the amended claims.
Examiner further notes that Wang was the first pertinent art cited in the pertinent prior art section across pages 10-12 of the office action dated May 8, 2025. Specific portions of paragraphs [0040], [0043], [0044], and [0061] of Wang were reproduced, and the specific claim language to which the aforementioned portions were relevant was conveyed, for the purposes of compact prosecution.
Applicant on page 13 argues: “Initially, Wang teaches that a chaining bit is in each instruction. The instant claim, by contrast, recites that an instruction hint is inserted into an instruction, not every instruction as Wang teaches, and that this is done only if a plurality of subsequent independent instructions are detected. In other words, if no subsequent instructions are detected, no hint is inserted. This is not the arrangement described in Wang, which clearly teaches that every instruction has a chaining bit.”
However, the claims do not appear to necessitate that an instruction hint is not inserted into every instruction. The claims also do not appear to necessitate that the insertion is done “only if” a plurality of subsequent independent instructions are detected. The claims also do not appear to necessitate that if no subsequent instructions are detected, no hint is inserted.
Applicant on page 13 argues: “Further, Wang teaches parallel instructions from multiple threads. By contrast, the instructions of the instant claim are all from the first thread. The plurality of subsequent independent instructions are all detected in the first thread, and not in an alternative or second thread, as in Wang.”
However, Examiner submits that Wang’s teaching of parallel instructions from multiple threads does not preclude Wang from also teaching detecting in a first thread of the plurality of threads a plurality of subsequent independent instructions, as cited.
Conclusion
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/KEITH E VICARY/Primary Examiner, Art Unit 2183