DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-12, and 14-21 are pending in this office action and presented for examination. Claims 1, 3, 11-12, 14, and 16 are newly amended, and claims 2 and 13 are newly cancelled, by the response received May 27, 2026.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
Paragraph [0053] of the amended specification received May 27, 2026, discloses “Fig. 2A is an example schematic illustration of a plurality of instructions of a thread scheduled for consecutive execution, utilized to describe an embodiment. In an embodiment, a plurality of instructions of a thread 210-1 through 210-N are processed consecutively (i.e., serially, in a non-pipelined manner), such that a first instruction thread 210-1 is completely processed before processing a second instruction thread 210-2”. However, Figure 2A, as well as other portions of the specification such as paragraph [0054] of the amended specification received May 27, 2026, refers to the elements associated with reference characters 210-1, 210-2, and 210-N as instructions rather than a thread or instruction threads. Therefore, the specification does not clearly set forth the invention.
Claim Objections
Claims 11-12 and 14-21 are objected to because of the following informalities. Appropriate correction is required.
In claim 11, line 14, it is unclear as to whether a hyphen or a strikethrough is present; in either case, the associated language would be unclear.
In claim 12, line 14, it is unclear as to whether a hyphen or a strikethrough is present; in either case, the associated language would be unclear.
Claims 14-21 are objected to for failing to alleviate the objection of claim 12 above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-10 and 19-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 8 recites the limitation “The method of claim 1, further comprising: generating the instruction hint to include a predetermined bit set to a value indicating that a next instruction is an independent instruction” in lines 1-3. Claim 1, upon which claim 8 is dependent, recites the limitation “inserting into the first thread an instruction hint, wherein the instruction hint is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and wherein the instruction hint, when read by an instruction scheduler of the processing circuitry, configures the instruction scheduler of the processing circuitry to serially execute the number of the plurality of subsequent independent instructions” in lines 7-12. However, the original disclosure (e.g., paragraph [0074], ‘where the write instruction is an "add" instruction, values from the first source register and the second source register are added and the result is written to a hardcoded register’; paragraph [0043], “an instruction hint bit [235] is selected and a value is applied to the instruction hint bit to indicate that a next instruction is an independent instruction”) does not appear to provide support for an instruction hint that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and includes a predetermined bit set to a value indicating that a next instruction is an independent instruction.
Claims 9-10 are rejected for failing to alleviate the rejection of claim 8 above.
Claim 9 recites the limitation “The method of claim 8, further comprising: detecting that the instruction is of a first category; and setting a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category” in lines 1-4. Claim 1, upon which claim 9 is indirectly dependent, recites the limitation “inserting into the first thread an instruction hint, wherein the instruction hint is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and wherein the instruction hint, when read by an instruction scheduler of the processing circuitry, configures the instruction scheduler of the processing circuitry to serially execute the number of the plurality of subsequent independent instructions” in lines 7-12. However, the original disclosure (e.g., paragraph [0074], ‘where the write instruction is an "add" instruction, values from the first source register and the second source register are added and the result is written to a hardcoded register’; paragraph [0079], paragraph [0080]) does not appear to provide support for an instruction hint, wherein the instruction is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and that is of a first category that is detected in order to set a number of predetermined bits to a value which indicates a number of next independent instructions.
Claim 10 is rejected for failing to alleviate the rejection of claim 9 above.
Claim 19 recites the limitation “The system of claim 12, wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: generate the instruction hint to include a predetermined bit set to a value indicating that a next instruction is an independent instruction” in lines 1-5. Claim 12, upon which claim 19 is dependent, recites the limitation “insert into the first thread an instruction hint, wherein the instruction hint is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and wherein the instruction hint, when read by an instruction scheduler of the processing circuitry, configures the instruction scheduler of the processing circuitry-to serially execute the number of the plurality of subsequent independent instructions” in lines 10-15. However, the original disclosure (e.g., paragraph [0074], ‘where the write instruction is an "add" instruction, values from the first source register and the second source register are added and the result is written to a hardcoded register’; paragraph [0043], “an instruction hint bit [235] is selected and a value is applied to the instruction hint bit to indicate that a next instruction is an independent instruction”) does not appear to provide support for an instruction hint that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and includes a predetermined bit set to a value indicating that a next instruction is an independent instruction.
Claims 20-21 are rejected for failing to alleviate the rejection of claim 19 above.
Claim 20 recites the limitation “The system of claim 19, wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to: detect that the instruction is of a first category; and set a number of predetermined bits to a value which indicates a number of next independent instructions based on the first category” in lines 1-6. Claim 12, upon which claim 20 is indirectly dependent, recites the limitation “insert into the first thread an instruction hint, wherein the instruction hint is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and wherein the instruction hint, when read by an instruction scheduler of the processing circuitry, configures the instruction scheduler of the processing circuitry-to serially execute the number of the plurality of subsequent independent instructions” in lines 10-15. However, the original disclosure (e.g., paragraph [0074], ‘where the write instruction is an "add" instruction, values from the first source register and the second source register are added and the result is written to a hardcoded register’; paragraph [0079], paragraph [0080]) does not appear to provide support for an instruction hint, wherein the instruction is an instruction that adds a number to a hardcoded register, the number indicating a number of the plurality of subsequent independent instructions, and that is of a first category that is detected in order to set a number of predetermined bits to a value which indicates a number of next independent instructions.
Claim 21 is rejected for failing to alleviate the rejection of claim 20 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 12 and 14-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the number of subsequent instructions of the second thread” in line 4. However, there is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “the processing circuitry” in line 13. However, it is indefinite as to whether the antecedent basis for this limitation is “a processing circuitry” in claim 12, line 3, or “a processing circuitry” in claim 12, line 7. Note that “the processing circuitry” is also recited in claim 12, line 14.
Claims 14-21 are rejected for failing to alleviate the rejection of claim 12 above.
Allowable Subject Matter
Claims 1, 3-4, and 6-7 are allowed.
Claim 11 would be allowed if the objection to claim 11 is overcome.
Response to Arguments
Applicant on page 1 argues: “The Title of the invention stands objected to as not descriptive. Following the Examiner's recommendation to incorporate subject matter of the last paragraph of claim 1, Applicant has amended the Title to read…”
In view of the aforementioned amendment, the previously presented objection to the title is withdrawn.
Applicant on page 2 argues: ‘Applicant has amended paragraphs [0053] and [0032] to refer to reference characters 210-1 through 210-N as "instructions of a thread" or "instructions," consistent with FIG. 2A and paragraph [0054]. The amendments resolve the inconsistency. No new matter is added. Withdrawal of the objection is respectfully requested.’
In view of the amendment to paragraph [0032], the associated facet of the specification objection is withdrawn. However, the amendment to paragraph [0053] does not appear to overcome a corresponding facet of the specification objection. For example, paragraph [0053] continues to disclose “first instruction thread 210-1” and “second instruction thread 210-2” in the last two lines. Examiner also notes that “210-1 through 210-N” may be understood to correspond to the nearest disclosed element “a thread” in lines 3-4.
Applicant on page 2 argues: “A Replacement Sheet 3 of 8 correcting this spelling is submitted herewith. Withdrawal of the objection is respectfully requested.”
In view of the aforementioned replacement sheet, the associated previously presented objection of the drawings is withdrawn.
Applicant on page 2 argues: “Claims 2 and 13 have been canceled without prejudice or disclaimer, rendering this rejection moot.”
In view of the aforementioned claim cancellations, the associated previously presented written description rejections are withdrawn.
Applicant on page 3 argues: ‘Applicant has amended claim 1 by replacing "an instruction scheduler" with "an instruction scheduler of the processing circuitry" so as to provide an antecedent basis for "the instruction scheduler of the processing circuitry." Independent claims 11 and 12 have been amended similarly.’
In view of the aforementioned amendment, the associated previously presented indefinite rejections of claims 1 and 11 are withdrawn. However, the associated rejection of claim 12 is not wholly overcome, in view of claim 12 reciting two separate instances of “a processing circuitry”, and the surrounding context of “the processing circuitry” in claim 12, lines 13 and 14. (Applicant may also want to provide antecedent basis clarity for recitations of “the processing circuitry” across claims 14 and 16-21 via explicit reference to a particular processing circuitry.)
Applicant on page 3 argues: ‘Claim 16 has been amended by replacing "the number of subsequent instructions of the second thread" with "the number of subsequent instructions."’
In view of the aforementioned amendment, the associated previously presented indefinite rejection is withdrawn.
Applicant across pages 3-4 argues: “Claim 1 has been amended by incorporating features from claim 2, and is therefore allowable over the cited references. Claims 11 and 12 have been amended similarly. Dependent claims 5-10 and 16-21 are also allowable over the cited references due to their dependency on an allowable base claim and their additional features.”
In view of the aforementioned amendments, the associated previously presented prior art rejections are withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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