DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
Method of producing a GaAs wafer by cleaving a material wafer at a position to produce an orientation flat
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 5-6, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Appl. Publ. No. 2006/0169988 to Kenya Itani (hereinafter “Itani”) in view of U.S. Patent Appl. Publ. No. 2022/0189883 to Itani, et al. (“Itani II”) and further in view of U.S. Patent Appl. Publ. No. 2022/0106702 to Eichler, et al. (“Eichler”).
Regarding claim 1, Itani teaches a method of producing a GaAs wafer (see the Abstract, Figs. 1A-D, ¶¶[0005]-[0013], and entire reference which teach a method of producing a GaAs wafer), comprising:
a grinding step of grinding a peripheral surface of a GaAs ingot including formation of a provisional orientation flat (see Fig. 1A and ¶[0009] which teach that a GaAs ingot includes an orientation flat (1a); see also ¶[0013] which teaches that the orientation flat is formed by grinding);
a slicing step of slicing the GaAs ingot after the grinding step to cut out a material wafer having an off angle (see Fig. 1A and ¶[0009] which teach that the GaAs ingot is sliced to produce a sliced wafer (1); see also ¶[0011] which teaches that the GaAs wafer has (100) as the principal plane which necessarily has at least a small degree of miscut since it is essentially impossible to make a wafer-sized substrate comprised entirely of the (100) plane); and
a cleaving step of applying marking to the material wafer according to an orientation of an orientation flat determined based on the provisional orientation flat and cleaving the material wafer toward a peripheral surface of the material wafer from the marking to form the orientation flat (see Figs. 1B-C, ¶[0009], and ¶[0011] which teach scribing the GaAs wafer to form a scratch (2) and cleaving along dotted line (3) to form a cleaved orientation flat along a (011) plane),
wherein the cleaving step is a step of cleaving the material wafer at a position where a length (interval A) of a line segment perpendicularly extended from the midpoint of the cleavage to the peripheral surface of the material wafer outward in a radial direction of the material wafer (see Figs. 1C and ¶[0009] which teach that the location of the cleavage plane along dotted line (3) produces a length of interval (A) which extends from a midpoint of the cleavage plane to the peripheral surface of the GaAs wafer (1)).
Itani does not teach that the length (A) is 9 mm or more. However, in Fig. 4 and ¶¶[0043]-[0057] Itani II teaches an analogous method of producing a plurality of wafers from an ingot of a Group III-V semiconductor such as InP by grinding an orientation flat and then slicing a plurality of wafers therefrom. In Fig. 1 and ¶¶[0029]-[0037] Itani II specifically teaches that the length of the ridge line (13) where the main surface (11) of the wafer (10) is in contact with the orientation flat is preferably between 8 to 50% of the diameter of the main surface (11) of the wafer in order to ensure that the location of the orientation flat can be efficiently confirmed while not taking up a significant portion of the total effective area of the wafer. Itani and Itani II do not teach that the wafer is a GaAs wafer with a diameter sufficient to produce a length A of 9 mm or more. However, in Fig. 1 and ¶¶[0055]-[0062] Eichler teaches that large diameter GaAs single crystal ingots may be produced by the vertical gradient freeze method. In at least Fig. 9, ¶[0006], ¶[0035], and ¶[0062] Eicher further teaches that present day GaAs wafers may have a diameter of 100, 150, or even as large as 200 mm. For a GaAs wafer having a diameter of 150 or 200 mm as taught by Eichler the length of the chord that constitutes the orientation flat can be up to 50% of the diameter as taught by Itani II which, upon performing some basic math for the geometry of a circle, translates to a chord length (i.e., the length of ridge line (13) in Fig. 1 of Itani II) of 75 or 100 mm and a length A of 10.0 mm and 13.4 mm, respectively. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to use the cleaving method of Itani on a 150 or 200 mm GaAs wafer as taught by Eichler to produce an orientation flat with a length of 75 or 100 mm and length A of 10 or 13.4 mm, respectively, as per the teachings of Itani II in order to reproducibly form large GaAs wafers with highly precise orientational flats for the production of electronic and optoelectronic devices thereupon. The combination of prior art elements according to known methods to yield predictable results has been held to support a prima facie determination of obviousness. All the claimed elements are known in the prior art and one skilled in the art could combine the elements as claimed by known methods with no change in their respective functions, with the combination yielding nothing more than predictable results to one of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S. 398, __, 82 USPQ2d 1385, 1395 (2007). See also, MPEP 2143(A).
Regarding claim 2, Itani does not teach that the interval A is 12 mm or more. However, as noted supra with respect to the rejection of claim 1, in Fig. 1 and ¶¶[0029]-[0037] Itani II specifically teaches that the length of the ridge line (13) where the main surface (11) of the wafer (10) is in contact with the orientation flat is preferably between 8 to 50% of the diameter of the main surface (11) of the wafer in order to ensure that the location of the orientation flat can be efficiently confirmed while not taking up a significant portion of the total effective area of the wafer. Then in Fig. 9, ¶[0006], ¶[0035], and ¶[0062] Eicher further teaches that present day GaAs wafers may have a diameter of up to 200 mm. For a GaAs wafer having a diameter of 200 mm the length of the chord that constitutes the orientation flat can be up to 50% of the diameter as taught by Itani II which translates to a chord length (i.e., the length of ridge line (13) in Fig. 1 of Itani II) of 100 mm and a length A of 13.4 mm whjich meets the claim. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to use the cleaving method of Itani on a 200 mm GaAs wafer as taught by Eichler to produce an orientation flat with a length of 100 mm and length A of 13.4 mm in order to reproducibly form large GaAs wafers with highly precise orientational flats for the production of electronic and optoelectronic devices thereupon.
Regarding claim 5, Itani and Itani II do not teach that the GaAs wafer has a diameter of 100 mm or more. However, as noted supra with respect to the rejection of claim 1, in Fig. 9, ¶[0006], ¶[0035], and ¶[0062] Eicher teaches that present day GaAs wafers may have a diameter of up to 200 mm. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to use a GaAs wafer having a diameter of up to 200 mm in order to benefit from the economies of scale and produce more electronic and/or optoelectronic devices per wafer.
Regarding claim 6, Itani and Itani II do not teach that the GaAs wafer has a diameter of 150 mm or more. However, as noted supra with respect to the rejection of claim 1, in Fig. 9, ¶[0006], ¶[0035], and ¶[0062] Eicher teaches that present day GaAs wafers may have a diameter of up to 200 mm. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to use a GaAs wafer having a diameter of up to 200 mm in order to benefit from the economies of scale and produce more electronic and/or optoelectronic devices per wafer.
Regarding claim 17, Itani and Itani II teach that the method produces a GaAs wafer group consisting of all GaAs wafers that are obtained from the GaAs ingot, that have an identical off angle, and that have the orientation flat formed by the cleaving step (see Figs. 1A-D and at least ¶¶[0009]-[0010] of Itani which teach that a single crystal ingot is sliced to produce a GaAs wafer (1) having an off-angle which is then cleaved to form an orientation flat; see also Fig. 4 and ¶¶[0042]-[0050] of Itani II which teach that a single ingot is sliced a plurality of times to produce a plurality of wafers; accordingly, a PHOSITA would be motivated to slice the GaAs ingot multiple times to produce a plurality of the same wafers (1) from a single ingot in order to make the production process more cost-effective), but do not explicitly teach that a mean value of orientation flat orientation accuracies of the GaAs wafer group is within ±0.010°, and a standard deviation of the orientation flat orientation accuracies of the GaAs wafer group is 0.009° or less. However, since the method of Itani, Itani II, and Eichler performs each and every step of the claimed process it must necessarily produce the same results, namely an orientation flat accuracy of ±0.010° and standard deviation of 0.009° or less as claimed. It is axiomatic that one who performs the steps of the known process must necessarily produce all of its advantages. Mere recitation of a newly discovered function or property, that is inherently possessed by things in the prior art does not cause a claim drawn to these things to distinguish over the prior art. Therefore, an orientation flat accuracy of ±0.010° and standard deviation of 0.009° or less, if not clearly envisaged, would be reasonably expected by the skilled artisan. See Leinoff v. Louis Milona & Sons, Inc. 220 USPQ 845 (CAFC 1984).
Claims 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itani in view of Itani II and further in view of Eichler and still further in view of U.S. Patent Appl. Publ. No. 2017/0204533 to Schunemann, et al. (“Schunemann”).
Regarding claim 3, Itani, Itani II, and Eichler do not teach that the off angle is 0.2° or more. However, in Fig. 6 and ¶¶[0054]-[0059] Schunemann teaches an embodiment of a system and method for epitaxial growth on wafers (212) such as GaAs. In ¶[0054] Schunemann specifically teaches that the GaAs wafer preferably has an off-cut angle of 2° to 4° in order to promote step-flow growth across the surface in order to produce a smoother surface with reduced defect incorporation and a 2 to 4 times increase in the growth rate during epitaxial growth. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to utilize a GaAs wafer with an off angle of 2° to 4° to promote step-flow growth and to increase the growth rate by 2 to 4 times such that the total growth time may be reduced.
Regarding claim 4, Itani, Itani II, and Eichler do not teach that an angle between a principal surface of the GaAs wafer and a surface forming the orientation flat is 89.80 or less or 90.2° or more. However, as noted supra with respect to the rejection of claim 3, in Fig. 6 and ¶¶[0054]-[0059] Schunemann teaches an embodiment of a system and method for epitaxial growth on wafers (212) such as GaAs. In ¶[0054] Schunemann specifically teaches that the GaAs wafer preferably has an off-cut angle of 2° to 4° in order to promote step-flow growth across the surface in order to produce a smoother surface with reduced defect incorporation and a 2 to 4 times increase in the growth rate during epitaxial growth. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to utilize a GaAs wafer with an off angle of 2° to 4° to promote step-flow growth and to increase the growth rate by 2 to 4 times such that the total growth time may be reduced. In this regard, when the off angle on the principal (100) surface of the sliced wafer (1) in Fig. 1 of Itani has an off-cut angle of 2° to 4° the cleavage surface (4) in Fig. 1D will necessarily form an angle with the (100) surface that is 89.8° or less or 90.2° or more as claimed. Stated in other words, since the combination of Itani, Itani II, and Eichler perform each and every step of the claimed process it must necessarily produce the same results, namely an angle between a principal surface of the GaAs wafer and a surface forming the orientation flat is 89.80 or less or 90.2° or more. It is axiomatic that one who performs the steps of the known process must necessarily produce all of its advantages. Mere recitation of a newly discovered function or property, that is inherently possessed by things in the prior art does not cause a claim drawn to these things to distinguish over the prior art. Therefore, an angle between a principal surface of the GaAs wafer and a surface forming the orientation flat of 89.80° or less or 90.2° or more, if not clearly envisaged, would be reasonably expected by the skilled artisan. See Leinoff v. Louis Milona & Sons, Inc. 220 USPQ 845 (CAFC 1984).
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itani in view of Itani II and further in view of Eichler and still further in view of U.S. Patent No. 5,110,764 to Nobuyoshi Ogino (“Ogino”).
Regarding claim 7, Itani teaches a beveling step of beveling a peripheral surface of the GaAs wafer except for the orientation flat, after the cleaving step (see ¶[0009] which teaches that the sliced wafer is chamfered (a form of beveling) such that the cleavage surface is remained). Even if it is assumed arguendo that the chamfering step of Itani is different from beveling, this would have been obvious in view of the teachings of Ogino. In at least Figs. 1-2 and col. 3, l. 7 to col. 4, l. 63 Ogino teaches a method of beveling circumferential edges of a wafer such that the beveled portions (1a) and (1b) have uneven widths and angles so that the former can prevent the occurrence of a crown and the latter can prevent the wafer from being chipped. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to bevel the peripheral surfaces of the GaAs wafer of Itani with the exception of the cleaved orientation flat in order to minimize the propensity for chipping of the wafer while still preserving the precision of the cleavage plane defined by the orientation flat.
Response to Arguments
Applicant's arguments filed April 30, 2026, have been fully considered but they are not persuasive.
Applicant’s proposed amendment to the title has been reviewed, but it remains overly generic and does not provide the casual reader with any indication as to the invention as disclosed and claimed in the instant application. A proposed replacement title has been provided by the Examiner.
Applicants initially argue that since Itani II forms the orientation flat (OF) by grinding an InP substrate and the disclosed 8 to 50% ratio is merely an arbitrary geometrical tolerance there is no motivation for a PHOSITA to combine the teachings of Itani and Itani II. See applicants’ 4/30/2026 reply, pp. 6-7. Applicant’s argument is noted, but is unpersuasive. The size of the orientation flat and, consequently, how much material is removed from the entire cross-sectional area of the sliced wafer is relevant regardless of whether the OF is formed by cleaving or by grinding. In this case ¶[0034] of Itani II specifically teaches that if the length of the ridge line (13) is less than 8% of the wafer diameter it may be difficult to confirm the existence of the OF and if the length of the ridge line (13) is more than 50% of the wafer diameter it reduces the effective area of the wafer. Thus, a PHOSITA would look to the teachings of Itani II and would be motivated to utilize an OF which is between 8 to 50% of the diameter of the main surface of the wafer in order to ensure that the location of the orientation flat can be readily confirmed while not taking up a significant portion of the total effective area of the wafer.
Applicant then argues that the length A is not recognized in the prior art as a routine variable subject to optimization. Id. at pp. 7-8. Applicant’s argument is noted, but is unpersuasive. In formulating the rejection of claim 1, the Examiner has not sought to optimize the length A, but instead is merely showing that the use of GaAs wafers with a diameter of 150 to 200 mm as taught by Eichler to produce an OF that is 50% of the diameter as taught by Itani II produces a length A of 10.0 mm and 13.4 mm, respectively.
Applicant subsequently argues that the claimed parameter of Interval A of 9 mm or more exhibits critical and unexpected results since ¶¶[0034]-[0035] and ¶[0040] of the specification teach that the standard deviation of the orientation sharply drops. Id. at pp. 8-9. Applicant’s argument is noted, but is unpersuasive. First, it is noted that a length A of “9 mm or more” does not encompass a narrow range, but instead encompasses the entire wafer from A = 9 mm to essentially the entire diameter of the wafer. Moreover, the cited sections of the specification do not appear to support the contention that there is a sudden improvement in the orientation accuracy when A = 9 mm or greater. Accordingly, this argument appears to be based on arguments of counsel rather than factually supported objective evidence.
Finally, applicant argues that Itani’s cleaving and Itani II’s grinding dimensions offer no guarantee or any reasonable expectation of successfully achieving the orientation accuracy as recited in new claim 17. Id. at p. 9. This argument also is found to be unpersuasive. As explained supra with respect to the rejection of claim 17, since the method taught by the combination of Itani, Itani II, and Eichler performs each and every step of the claimed process it must necessarily produce the same results, namely an OF orientation accuracy of within ±0.010° and a standard deviation of the OF orientation accuracies of 0.009° or less as claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KENNETH A BRATLAND JR/Primary Examiner, Art Unit 1714
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