DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11-12, and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (WO 2020/262320) (“Ito”) (US 2022/0353449 used as English translation).
With regard to claim 1, fig. 14 of Ito discloses an imaging element comprising: a first semiconductor substrate 100 including a photoelectric conversion section PD that performs photoelectric conversion of incident light; a second semiconductor substrate 20 including a pixel circuit (22, 21) that generates an image signal corresponding to a charge generated by the photoelectric conversion PD, the second semiconductor substrate 20 stacked with the first semiconductor substrate 10 on a back side of the second semiconductor substrate(bottom of 20); an insulating layer 46 disposed between the first semiconductor substrate 10 and the second semiconductor substrate 20; a connection section 54 penetrating through the insulating layer 46 and connecting the first semiconductor substrate 10 and the back side of the second semiconductor substrate 20; and a recess (“low-permittivity region 90A may be configured as an air gap”, par [0265]) disposed on a surface of the insulating layer 46 adjacent to the second semiconductor substrate 20, the recess (“air gap”, par [0265]) formed around (“low-permittivity region 90A may be provided over the entire periphery to surround the circumference of the through-wiring line 54”, par[0263]) the connection section 54.
With regard to claim 2, fig. 14 of Ito discloses that the connection section 54 makes reference potentials FD of the first semiconductor substrate 10 and the second semiconductor substrate 20 common.
With regard to claim 3, fig. 14 of Ito discloses that the recess 90A forms a gap (“air gap”, par [0265]) with the back side of the second semiconductor substrate 20.
With regard to claim 4, fig. 14 of Ito discloses the gap 90A is a vacuum (“low-permittivity region 90A may be configured as an air gap of which the inside is a vacuum”, par [0265]).
With regard to claim 5, fig. 14 of Ito discloses that the recess 90A is formed in the insulating layer 46 in a region different from a region immediately below an element (22, 21) formed in the second semiconductor substrate 20.
With regard to claim 6, fig. 14 of Ito discloses that wiring (lower portion of 54) disposed in the insulating layer 46 and connected to the first semiconductor substrate 10, wherein the recess 90A is formed in the insulating layer 46 in a region different from a region in which the wiring (lower portion of 54) is disposed.
With regard to claim 7, fig. 14 of Ito discloses that the recess (“low-permittivity region 90A may be configured as an air gap”, par [0265]) is formed in common around a plurality of the connection sections 54.
With regard to claim 8, figs. 10 and 14 of Ito discloses that the recess 90A is formed in a band shape.
With regard to claim 11, fig. 14 of Ito discloses that the connection section 54 contains silicon (“metal wiring line may be provided with a barrier layer of silicon carbide (SiC)”, par [0261]).
With regard to claim 12, fig. 14 of Ito discloses that the insulating layer 46 is made of an oxide (“silicon oxide”, par [0265]).
With regard to claim 14, fig. 14 of Ito discloses a pad FD disposed adjacent to the first semiconductor substrate 10, wherein the connection section 54 is connected to the first semiconductor substrate 10 via the pad FD.
With regard to claim 15, fig. 14 of Ito discloses comprising a semiconductor region FD formed by diffusion of an impurity contained in the pad FD into the first semiconductor substrate 10.
With regard to claim 16, figs. 14 and 67 of Ito discloses that the pixel circuit (“amplification transistor”, par [0618]) includes a FinFET (“Fin type”, par [0618]).
With regard to claim 17, figs. 1 and 14 of Ito discloses an imaging element comprising: a first semiconductor substrate 100 including a photoelectric conversion section PD that performs photoelectric conversion of incident light; a second semiconductor substrate 20 including a pixel circuit (22, 21) that generates an image signal corresponding to a charge generated by the photoelectric conversion PD, the second semiconductor substrate 20 stacked with the first semiconductor substrate 10 on a back side of the second semiconductor substrate(bottom of 20); an insulating layer 46 disposed between the first semiconductor substrate 10 and the second semiconductor substrate 20; a connection section 54 penetrating through the insulating layer 46 and connecting the first semiconductor substrate 10 and the back side of the second semiconductor substrate 20; and a recess (“low-permittivity region 90A may be configured as an air gap”, par [0265]) disposed on a surface of the insulating layer 46 adjacent to the second semiconductor substrate 20, the recess (“air gap”, par [0265]) formed around (“low-permittivity region 90A may be provided over the entire periphery to surround the circumference of the through-wiring line 54”, par[0263]) the connection section 54; and a processing circuit 34 that processes the image signal that has been generated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (WO 2020/262320) (“Ito”) (US 2022/0353449 used as English translation) in view of Haneda (WO 2020/004065) (US 2021/0118935 used as English translation).
With regard to claim 9, Ito does not disclose that the recess has a depth deeper than or equal to 5 nm.
However, fig. 4D of Haneda discloses that the recess 150 has a depth deeper than or equal to 5 nm (“recess formed in the first inter-wiring insulating layer 120 may have, for example, a depth of 30 nm”, par [0073]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the air gap of Ito with the depth of 30 nm as taught in Haneda in order to reduce the inter-wring capacitance of the wiring layer. See par [0056] of Haneda.
With regard to claim 10, Ito does not disclose that the connection section has a height greater than or equal to 5 nm from a bottom surface of the recess.
However, fig. 4D of Haneda discloses that the connection section 130 has a height greater than or equal to 5 nm (“recess formed in the first inter-wiring insulating layer 120 may have, for example, a depth of 30 nm”, par [0073]) from a bottom surface of the recess 150.
Therefore, it would have been obvious to one of ordinary skill in the art to form the air gap of Ito with the depth of 30 nm as taught in Haneda in order to reduce the inter-wring capacitance of the wiring layer. See par [0056] of Haneda.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893