DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shatalov et al. (US 9818826).
Regarding claim 1, Shatalov discloses a substrate for a semiconductor device, the substrate comprising:
a semiconductor wafer (12, fig. 3 and Col. 7);
an intermediate nanowire layer (40, fig. 3 and Col. 7) having a plurality of nanowires each having in succession a base portion mounted to the semiconductor wafer, an elongated body portion extending away from the semiconductor wafer, and a tip portion (figs. 3, 5-13); and
a buffer layer of aluminum nitride being made integral to the tip portions of the plurality of nanowires (42, fig. 3 and Col. 7).
Regarding claim 2, Shatalov further discloses wherein the buffer layer of aluminum nitride has a thickness ranging between about 20 nm and about 2 µm (Col. 7).
Regarding claim 3, Shatalov further discloses wherein the buffer layer of aluminum nitride is at least one of metal-polar and non-metal polar (Cols. 7-8).
Regarding claim 4, Shatalov further discloses wherein the buffer layer of aluminum nitride is at least one of nitrogen-polar and aluminum-polar (Cols. 7-8).
Regarding claim 5, Shatalov further discloses an epilayer of a semiconductor material deposited on the buffer layer of aluminum nitride (16, fig. 3 and Col. 5).
Regarding claim 6, Shatalov further discloses wherein the epilayer is at least one of nitrogen-polar and aluminum-polar (Col. 5).
Regarding claim 7, Shatalov further discloses wherein the semiconductor material of the epilayer is a group-III nitride semiconductor (Col. 5).
Regarding claim 8, Shatalov further discloses wherein the semiconductor material is aluminum gallium nitride (Col. 5).
Regarding claim 9, Shatalov further discloses wherein the aluminum gallium nitride has an aluminum content varying between ~35% and ~70% (Col. 5).
Regarding claim 10, Shatalov further discloses wherein the semiconductor wafer is a silicon wafer (Col. 5).
Regarding claim 11, Shatalov further discloses wherein the nanowires are made of gallium nitride (Col. 5).
Regarding claim 12, Shatalov further discloses wherein the nanowires are grown in a self-organized manner with respect to the semiconductor wafer (Cols. 13-15).
Regarding claim 13, Shatalov further discloses wherein said buffer layer has a plurality of coalescence boundaries running within the buffer layer and terminating short of a distal face of the buffer layer (fig. 3 and Cols. 7-8).
Regarding claim 14, Shatalov further discloses wherein said nanowires have a cross-sectional area increasing from the semiconductor wafer to the buffer layer (fig. 6A, top section).
Regarding claim 15, Shatalov further discloses a base layer of aluminum nitride atop the semiconductor wafer, the intermediate nanowire layer being mounted to the base layer of aluminum nitride (86, fig. 12 and Col. 14).
Regarding claim 16, Shatalov further discloses wherein the base layer has a thickness ranging between about 0.5 nm and 10 nm (Col. 14).
Regarding claim 18, Shatalov discloses a method of manufacturing a substrate for a semiconductor device, the method comprising:
growing a plurality of nanowires on a semiconductor wafer (12, fig. 3 and Col. 7), the nanowires having in succession a base portion mounted to the semiconductor wafer, an elongated body portion extending away from the semiconductor wafer, and a tip portion (40, fig. 3 and Col. 7); and
making a buffer layer of aluminum nitride integral to the tip portions of the plurality of nanowires (42, fig. 3 and Col. 7).
Regarding claim 19, Shatalov further discloses wherein said making is performed under environmental conditions slowing aluminum adatom migration within the buffer layer, said making including making the buffer layer with a non-metal surface termination (Col. 14).
Claim 43 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weman et al. US 2015/0194549.
Regarding claim 43, Weman discloses a substrate for a semiconductor device, the substrate comprising:
a semiconductor wafer (figs. 3A, 5A-B and paragraph 0218);
an intermediate nanowire layer having a plurality of nanowires each having in succession a base portion mounted to the semiconductor wafer, an elongated body portion extending away from the semiconductor wafer, and a tip portion (figs. 3A, 5A-B and paragraphs 0205-0210); and
a graphene electrode being made integral to the tip portions of the plurality of nanowires (fig. 5b and paragraph 0210).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shatalov et al. (US 9818826) in view of Weman et al. (US 2015/0194549).
Regarding claim 17, Shatalov discloses the substrate of claim 1 as mentioned above. Shatalov further discloses the use of electrodes (Cols. 5-6). Shatalov does not explicitly discloses wherein the electrode comprises graphene. However, the use of graphene for electrode purposes in nanowire structures was well known at the time of filing and would therefore have been deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate such known use of graphene as an electrode see Weman (fig. 5b and paragraph 0210).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2018/0204977 discloses a relevant nanowire structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 12/27/25