Prosecution Insights
Last updated: April 19, 2026
Application No. 18/550,726

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

Non-Final OA §102§103§112
Filed
Sep 15, 2023
Examiner
AHMED, SHAHED
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
866 granted / 955 resolved
+22.7% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
45 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 955 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to application No. 18550726 filed on 09/15/2023. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Allowable Subject Matter Claims 9-20 are allowed. The following is an examiner' s statement of reasons for allowance: Claims 9-12: The primary reason for the allowance of the claims is the inclusion of the limitation “injecting the cooling medium into a region surrounded by the adhesive”, in all of the claims in combination with the remaining features of independent claim 9. Claims 13-16: The primary reason for the allowance of the claims is the inclusion of the limitation “injecting the cooling medium into a clearance formed by the substrate, the adhesive, and the semiconductor element”, in all of the claims in combination with the remaining features of independent claim 13. Claims 17, 20: The primary reason for the allowance of the claims is the inclusion of the limitation “placing metal-coated small spheres on a plurality of recesses provided on a substrate”, in all of the claims in combination with the remaining features of independent claim 17. Claim 18: The primary reason for the allowance of the claims is the inclusion of the limitation “placing metal-coated small spheres on a plurality of soldering pads disposed on a substrate”, in all of the claims in combination with the remaining features of independent claim 18. Claim 19: The primary reason for the allowance of the claims is the inclusion of the limitation “placing metal-coated small spheres on a plurality of soldering pads disposed on a lower surface of a semiconductor element”, in all of the claims in combination with the remaining features of independent claim 19. Hirokazu (JP 2010129827 A) teaches a method for manufacturing a semiconductor device, comprising: applying an adhesive (Fig. 1, element 30) in such a manner as to surround a region on a substrate (Fig. 1, element 20) where a cooling medium (Fig. 1, elements 321 & 322) is disposed; and adhering a semiconductor (Fig. 1, element 10) element onto the adhesive. However, Hirokazu does not teach or render obvious the above-quoted features recited in independent claims 9, 13, 17, 18, 19. Claims 2-4, 7 are objected to as being dependent upon a rejected base claim (independent claim 1), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner' s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Hirokazu (JP 2010129827 A). With respect to dependent claim 2, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the cooling medium is a liquid metal”. With respect to dependent claim 3, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the cooling medium is a metal-coated small sphere”. With respect to dependent claim 4, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the cooling medium is a liquid metal and a metal-coated small sphere”. With respect to dependent claim 7, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein the clearance is formed by the substrate, the semiconductor element, and an adhesive applied to an entire peripheral edge of the semiconductor element to fix both the substrate and the semiconductor element, and a partition having a height lower than a thickness height of the adhesive protrudes from an upper surface of the substrate along an inner periphery of the adhesive”. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 6 recites the limitation “a low surface tension material”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The specification does not define what constitutes “a low surface tension material” and therefore this limitation is unclear. For the purpose of the examination, the elements 321 & 322 are interpreted as “a low surface tension material”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 5-6, 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirokazu (JP 2010129827 A). Regarding independent claim 1, Hirokazu teaches a semiconductor device, comprising: a semiconductor element (Fig. 1, element 10); a substrate (Fig. 1, element 20) to which the semiconductor element is fixed; and a cooling medium (Fig. 1, elements 321 & 322) with which a clearance (Fig. 1) formed when the semiconductor element and the substrate are fixed (Fig. 1, element 10 and 20 are fixed to each other by adhesive 30) to each other is filled. Regarding claim 5, Hirokazu teaches wherein the cooling medium with which the clearance is filled is disposed below a heat generating source (Fig. 1, the semiconductor element 10 generates heat when it is ON) of the semiconductor element. Regarding claim 6, Hirokazu teaches wherein the clearance is formed by the substrate, the semiconductor element, and an adhesive applied to an entire peripheral edge of the semiconductor element to fix both the substrate and the semiconductor element, and an upper surface of the substrate is covered with a low surface tension material along an inner periphery of the adhesive (Fig. 1). Regarding independent claim 21, Hirokazu teaches an electronic apparatus having a semiconductor device, comprising: a semiconductor element (Fig. 1, element 10); a substrate (Fig. 1, element 20) to which the semiconductor element is fixed fixed (Fig. 1, element 10 and 20 are fixed to each other by adhesive 30); and a cooling medium (Fig. 1, elements 321 & 322) with which a clearance (Fig. 1) formed when the semiconductor element and the substrate are fixed to each other is filled. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hirokazu (JP 2010129827 A) in view of Kazuo et al. (JP H06177299 A). Regarding claim 8, Hirokazu teaches all of the limitations as discussed above. Hirokazu does not explicitly disclose further comprising a heat exhausting mechanism on a lower surface of the substrate. Kazuo et al. teach a semiconductor device comprising a heat exhausting mechanism on a lower surface of the substrate (Claim 12). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Hirokazu according to the teachings of Kazuo et al. with the motivation to “excluding heat on a surface opposite to a board mounting surface”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Sep 15, 2023
Application Filed
Nov 10, 2025
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604673
JOSEPHSON JUNCTION DEVICE AND METHOD OF MAKING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604589
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604498
MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12604502
NANOCHANNEL GALLIUM NITRIDE-BASED DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 14, 2026
Patent 12598762
METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION AND A SEMICONDUCTOR DEVICE WITH LOCAL ISOLATION
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
91%
With Interview (+0.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 955 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month