Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-4, 6-12 and 14-15 are rejected under 35 U.S.C. 102(a1) as being anticipated by Hayasaki et al. (US 2010/0327383; hereinafter Hayasaki).
Regarding claim 1, Hayasaki, in fig. 2, discloses a semiconductor device comprising: a stack (10/25/27/30/40/32) including a semiconductor substrate 10; an opening 41 provided extending from a first surface 32 of the stack (10/25/27/30/40/32) and filled with an insulating material 11; a pad electrode 29B provided at a bottom of the opening 41; a wiring layer (28A/29A) provided in a planar region 27 of the stack (10/25/27/30/40/32) overlapping a planar region 27 where the opening 41 is provided in plan view from the first surface 32, the wiring layer (28A/29A) being electrically connected to the pad electrode 29B; and a through electrode (36/37) provided in a planar region (10/25) different from the planar region 27 where the opening 41 is provided in the plan view and provided extending from a second surface 10 of the stack (10/25/27/30/40/32) opposite to the first surface 32.
Regarding claim 2, Hayasaki discloses wherein the stack (10/25/27/30/40/32) includes a first substrate (27/30/40/32) adjacent to the first surface 32 and a second substrate (10/25) adjacent to the second surface 10, the first substrate (27/30/40/32) and the second substrate (10/25) being stacked (fig. 2).
Regarding claim 3, Hayasaki discloses wherein the first substrate (27/30/40/32) includes a first semiconductor substrate 30 and a first multilayer wiring layer 28A/29A stacked on the first semiconductor substrate 30, the second substrate (10/25) includes a second semiconductor substrate 10 and a second multilayer wiring layer 24A/26A stacked on the second semiconductor substrate 10, and the first substrate (27/30/40/32) and the second substrate (10/25) are stacked with the first multilayer wiring layer 28A/29A and the second multilayer wiring layer 24A/26A facing each other (fig. 2).
Regarding claim 4, Hayasaki discloses wherein the pad electrode 29B is provided inside the first multilayer wiring layer 28A/29A (fig. 2).
Regarding claim 6, Hayasaki discloses further comprising an electrode bonding structure (26A/39) provided at an interface between the first multilayer wiring layer (28A/29A) and the second multilayer wiring layer 26A, the electrode bonding structure (26A/39) bonding metal electrodes exposed at the interface (fig. 2).
Regarding claim 7, Hayasaki discloses further comprising a pixel array unit provided on the first surface of the stack, the pixel array unit including a plurality of pixels two-dimensionally arranged therein ([0026]).
Regarding claim 8, Hayasaki discloses wherein the pad electrode 29B and the through electrode 36/37 are provided on an outer periphery of the pixel array unit (fig. 2).
Regarding claim 9, Hayasaki discloses wherein the through electrode 36/37 is provided in a planar region 10/25 adjacent to a side of the pad electrode 29B remote from the pixel array unit (fig. 2).
Regarding claim 10, Hayasaki discloses further comprising a transparent substrate 12 stacked over the first surface (27/30/40/32) of the stack (10/25/27/30/40/32) (fig. 2).
Regarding claim 11, Hayasaki discloses wherein a gap 34 is formed between the stack (10/25/27/30/40/32) and the transparent substrate 12 (fig. 2).
Regarding claim 12, Hayasaki discloses wherein the pad electrode 29B is provided extending from a planar region overlapping the planar region where the opening 41 is provided to the planar region where the through electrode (36/37) is provided (fig. 2).
Regarding claim 14, Hayasaki discloses wherein the through electrode (36/37) is electrically connected to an external connection part 18 through a wiring provided along the second surface 10 ([0023]-[0024] & figs. 1-2).
Regarding claim 15, Hayasaki discloses further comprising a protection element 36 provided in a planar region of the stack (10/25/27/30/40/32) overlapping the planar region where the opening 41 is provided in the plan view and electrically connected to the pad electrode 29B (fig. 2).
2. Claims 1-5 and 7-15 are rejected under 35 U.S.C. 102(a2) as being anticipated by Kazue (US 11,699,653).
Regarding claim 1, Kazue, in fig. 4, discloses a semiconductor device comprising: a stack 71/74 including a semiconductor substrate 71/74; an opening 73 provided extending from a first surface 23b of the stack 71/74 and filled with an insulating material 32; a pad electrode PAD provided at a bottom of the opening 73; a wiring layer 26 provided in a planar region 71 of the stack 71/74 overlapping a planar region 71 where the opening 73 is provided in plan view from the first surface 23b, the wiring layer 26 being electrically connected to the pad electrode PAD; and a through electrode 11/14 provided in a planar region 74 different from the planar region 71 where the opening 73 is provided in the plan view and provided extending from a second surface 25b of the stack 71/74 opposite to the first surface 23b.
Regarding claim 2, Kazue discloses wherein the stack 71/74 includes a first substrate 71 adjacent to the first surface and a second substrate 74 adjacent to the second surface, the first substrate 71 and the second substrate 74 being stacked (fig. 4).
Regarding claim 3, Kazue discloses wherein the first substrate 71 includes a first semiconductor substrate and a first multilayer wiring layer 26 stacked on the first semiconductor substrate, the second substrate 74 includes a second semiconductor substrate and a second multilayer wiring layer 27 stacked on the second semiconductor substrate, and the first substrate and the second substrate are stacked with the first multilayer wiring layer 26 and the second multilayer wiring layer 27 facing each other (fig. 4).
Regarding claim 4, Kazue discloses wherein the pad electrode PAD is provided inside the second multilayer wiring layer (fig. 4).
Regarding claim 5, Kazue discloses wherein the first semiconductor substrate 71 includes a photoelectric conversion element PD that photoelectrically converts light incident on the first surface (fig. 4).
Regarding claim 7, Kazue discloses further comprising a pixel array unit 114 provided on the first surface of the stack, the pixel array unit 114 including a plurality of pixels two-dimensionally arranged therein (fig. 6).
Regarding claim 8, Kazue discloses wherein the pad electrode PAD and the through electrode 11/14 are provided on an outer periphery of the pixel array unit (fig. 4).
Regarding claim 9, Kazue discloses wherein the through electrode 11/14 is provided in a planar region adjacent to a side of the pad electrode PAD remote from the pixel array unit (fig. 4).
Regarding claim 10, Kazue discloses further comprising a transparent substrate 40 stacked over the first surface 23 of the stack 71/74 (fig. 4).
Regarding claim 11, Kazue discloses wherein a gap 30/31 is formed between the stack 71/74 and the transparent substrate 40 (fig. 4).
Regarding claim 12, Kazue discloses wherein the pad electrode PAD is provided extending from a planar region overlapping the planar region where the opening 73 is provided to the planar region where the through electrode 11/14 is provided (fig. 4).
Regarding claim 13, Kazue discloses wherein a probe mark appears on a surface of the pad electrode facing the opening (col. 8, lines 40-47).
Regarding claim 14, Kazue discloses wherein the through electrode 11/14 is electrically connected to an external connection part through a wiring provided along the second surface (fig. 4 & col. 11, lines 9-23).
Regarding claim 15, Kazue discloses further comprising a protection element 13 provided in a planar region of the stack overlapping the planar region where the opening is provided in the plan view and electrically connected to the pad electrode PAD (fig. 4).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID VU/
Primary Examiner, Art Unit 2818