DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hynecek (United States Patent Application Publication No. US 2018/0308881 A1, hereinafter “Hynecek”).
In reference to claim 1, Hynecek discloses a device which meets the claim. Fig. 2 of Hynecek discloses a sensor device which comprises a first substrate unit (101) and a second substrate unit (301) bonded to the first substrate unit (101). The first substrate unit (101) includes a first semiconductor substrate (101) and a pixel region (102) provided on the first semiconductor substrate (101) in which an SPAD pixel (101 - right side) and a plurality of visible-light pixels (101 - left side) are mixed in an array. The second substrate unit (301) includes a second semiconductor substrate (309) facing the first semiconductor substrate (101). An SPAD circuit (ASIC – right side) is provided on the second semiconductor substrate (301) and is connected to the SPAD pixel (101 – right side). A visible-light pixel circuit (ASIC – left side) is provided on the second semiconductor substrate (301) and is connected to the plurality of visible-light pixels (101 – left side).
With regard to claim 2, the second semiconductor substrate (301) includes a first circuit region (311) which overlaps a position of the pixel region (102) in a direction in which the first semiconductor substrate (101) and the second semiconductor substrate (301) face each other. There is a second circuit region (310) positioned around the first circuit region (311) and does not overlap the position of the pixel region (102) in the direction in which the first semiconductor substrate (101) and the second semiconductor substrate (301) face each other. The SPAD circuit (ASIC – right side) is disposed in the first circuit region (311). The visible-light pixel circuits (ASIC – left side) are disposed in the second circuit region (310).
In reference to claim 3, the first substrate unit (101) includes a first wiring layer (205, 206, 207, Ox - 201) provided on a surface of the first semiconductor substrate (101) with the surface facing the second semiconductor substrate (301). The second substrate unit (301) includes a second wiring layer (302, 303, 304, Ox - 301) provided on a surface of the second semiconductor substrate (301) with the surface facing the first semiconductor substrate (101). The first wiring layer (205, 206, 207, Ox) includes a first wiring line (205 – right side) connected to the SPAD pixel (101 – right side) and a second wiring line (205 – left side) connected to the plurality of visible-light pixels (101 – left side). The second wiring layer 302, 303, 304, Ox) includes a third wiring line (303 – right side) connected to the SPAD circuit (ASIC – right side), and a fourth wiring line (303 – left side) connected to the visible-light pixel circuit (ASIC – left side). The SPAD pixel (101 – right side) and the SPAD circuit (ASIC – right side) are connected to each other via the first wiring line (205 – right side( and the third wiring line (303 – right side). The plurality of visible-light pixels (101 – left side) and the visible-light pixel circuit (ASIC – left side) are connected to each other via the second wiring line (205 – left side) and the fourth wiring line (303 – left side).
With regard to claim 9, there is a plurality of SPAD pixels (101 – right side) disposed in the pixel region (102). A plurality of SPAD circuits (ASIC – right side) are disposed in the second semiconductor substrate (301) corresponding to the plurality of SPAD pixels (101 – right side).
In reference to claim 11, a lens body (116) is disposed on an opposite side of the second semiconductor substrate (301) with the first semiconductor substrate (101) interposed between them. An optical filter (112) is disposed between the SPAD pixel (101 – right side) and the lens body (116). The optical filter (112) is a visible light filter which transmits light having a preset wavelength and blocks light other than the light having the preset wavelength.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over by Hynecek in view of Chen et al. (United States Patent Application Publication No. US 2015/0279816 A1, hereinafter “Chen”).
With regard to claim 4, fig. 2 of Hynecek shows that the first wiring layer (205, 206, 207, Ox - 201) includes a first interlayer insulation film (Ox – 201) and the second wiring layer (302, 303, 304, Ox - 301) includes a second interlayer insulation film (Ox – 301) bonded to the first interlayer insulation film (Ox – 201). On a bonding plane between the first interlayer insulation film (Ox – 201) and the second interlayer insulation film (Ox - 301), the first wiring line (207 – right side) and the third wiring line (302 – right side) are bonded by hybrid bonding (p. 2, paragraph 25) between the metal materials of the first wiring line (207 – right side) and the third wiring line (302 – right side). The second wiring line (207 – left side) and the fourth wiring line (302 – left side) are bonded by hybrid bonding (p. 2, paragraph 25) between the metal materials of the second wiring line (207 – left side) and the fourth wiring line (302 – left side). Hynecek does not disclose that the metal for the first, second, third, and fourth wiring lines are made of copper (Cu) as part of the hybrid bond. However Chen discloses that copper is a suitable conductor for use as a hybrid bonding material (p. 2, paragraph 18). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to use copper as the metal for the first, second, third, and fourth wiring lines as part of the hybrid bond.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over by Hynecek in view of Shinohara (United States Patent Application Publication No. US 2012/0033119 A1, hereinafter “Shinohara”).
With regard to claim 5, fig. 2 of Hynecek shows that the first semiconductor substrate (101) includes a first element isolation unit (104) positioned between the SPAD pixel (101 – right side) and the visible-light pixel (101 – left side). Although not shown, it is understood that a second element isolation unit (104) is positioned between one visible-light pixel (101 – left side) and another visible-light pixel (101 – left side) adjacent to each other among the plurality of visible-light pixels (101 – left side) since the small portion of the device shown in fig. 2 is a part of an array. The first element isolation unit (104) is provided on the first semiconductor substrate (101) and the second element isolation unit (104) is provided on the first semiconductor substrate (101). Hynecek does not disclose that the first and second isolation units (104) include respective first and second trenches. However fig. 11A-11B of Shinohara disclose the use of an isolation unit in the form of a trench (42) with a light-shielding film (73). Shinohara discloses that such a form of isolation leads to improved sensitivity (p. 7, paragraph 101) which is a known goal in the art (p. 1, paragraphs 5, 12, and 13). In view of Shinohara, it would therefore be obvious to implement the first and second isolation units of Hynecek with first and second trenches.
In reference to claim 6, in the device of Hynecek constructed in view of Shinohara, the first isolation unit (104) includes a light-shielding film (73) disposed in the first trench.
With regard to claim 7, neither Hynecek nor Shinohara disclose that the first trench is wider than the second trench. Although Hynecek nor Shinohara teach the relative widths of the first and second trenches as that claimed by the applicant:
Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Size and dimension differences are generally not sufficient to patentably distinguish from the prior art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").
In view of the above, adjusting the relative widths of the first and second trenches to optimal values is considered to be obvious to one with ordinary skill in the art. Therefore this limitation is not patentable over Hynecek and Shinohara.
With regard to claim 8, fig. 2 of Hynecek shows that the first semiconductor substrate (101) includes an isolation structure (104) provided on a surface of the first semiconductor substrate (101) that faces the second semiconductor substrate (301) and surrounds the SPAD pixel (101 – right side). Hynecek does not disclose that the isolation structure (104) includes a light-shielding wall part. However fig. 11A-11B of Shinohara disclose the use of an isolation structure unit in the form of a trench (42) with a light-shielding wall (73). Shinohara discloses that such a form of isolation leads to improved sensitivity (p. 7, paragraph 101) which is a known goal in the art (p. 1, paragraphs 5, 12, and 13). In view of Shinohara, it would therefore be obvious to implement the isolation structure of Hynecek with a light-shielding wall part.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over by Hynecek in view of Kwiatkowski et al. (USPN 7,309,878 B1, hereinafter “Kwiatkowski”).
In reference to claim 10, the small portion of the device shown in fig. 2 of Hynecek is a part of an array. Thus there is a plurality of SPAD pixels (101 – right side) disposed at regular intervals in a first direction and second direction orthogonal to the first direction. A disposition interval of the SPAD pixels (101 – right side) in the first direction is a first pitch length and a disposition interval of the SPAD pixels (101 – left side) in the second direction is a second pitch length. In fig. 2 of Hynecek, a product of the first pitch length and the second pitch length is at least equal to the unit area of a pixel. Hynecek does not explicitly disclose that an area of one the SPAD circuit (ASIC – right side) is equal to or smaller than a product of the first pitch length and the second pitch length. However Kwiatkowski discloses that making the signal processing circuitry small enough to fit within the unit area of pixel increases the functionality/processing sophistication of the circuitry (column 1, lines 65-67, column 2, lines 1-12) which is desirable in the art (column 1, lines 41-64). In view of Kwiatkowski, it would therefore be obvious to implement the SPAD circuit disclosed by Hynecek such that it fits within the SPAD pixel unit area. In the device of Hynecek constructed in view of Kwiatkowski, an area of one of the SPAD circuit (ASIC – right side) is equal to the unit area of a pixel. As noted above with regard to fig. 2 of Hynecek, a product of the first pitch length and the second pitch length is at least equal to the unit area of a pixel. Thus claim 10 is not patentable over Hynecek and Kwiatkowski.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over by Hynecek in view of Eminoglu et al. (United States Patent Application Publication No. US 2010/0140732 A1, hereinafter “Eminoglu”).
In reference to claim 12, fig. 2 of Hynecek discloses that the SPAD circuit (ASIC – right side) is disposed on the second semiconductor substrate (301). Fig. 2 of Hynecek does not disclose a third substrate unit disposed on an opposite side of the first substrate unit (101) with the second substrate unit (301) interposed between them such that a part of the SPAD circuit is disposed on the second semiconductor substrate (301) and the third substrate unit includes a third semiconductor substrate with another part of the SPAD circuit disposed on it. However fig. 3 of Eminoglu discloses the use of chip stacking (p. 3, paragraph 31) in order to incorporate separate chips (310, 340) with high voltage and low voltage circuitry in order to attain an image sensor with a high dynamic range (p. 3, paragraph 18) which is desirable in the art (p. 1-2, paragraphs 7-10). In view of Eminoglu, it would therefore be obvious to implement the SPAD circuit of Hynecek with two separate stacked semiconductor substrates with the second semiconductor substrate having high voltage SPAD circuitry and the third semiconductor substrate having low voltage SPAD circuitry.
With regard to claim 13, in the device of Hynecek constructed in view of Eminoglu, the part of the SPAD circuit is a circuit to which a high voltage is applied, and the another part of the SPAD circuit is a circuit to which a low voltage is applied.
Conclusion
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893