Prosecution Insights
Last updated: April 19, 2026
Application No. 18/551,263

EPITAXIAL STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Sep 19, 2023
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Dynax Semiconductor Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
86%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
710 granted / 837 resolved
+16.8% vs TC avg
Minimal +1% lift
Without
With
+1.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.7%
+7.7% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
14.4%
-25.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 837 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1-12 are objected to because of the following informalities: claim 1, line 6 contains the phrase, “arranged in stack,” which is grammatically incorrect. Appropriate correction is required. The examiner believes that the above phrase should read arranged in a stack and has thus interpreted the claim in this manner. Dependent claims 2-12 are also objected to due to their dependency. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 4-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (United States Patent Application Publication No. US 2014/0370634 A1, hereinafter “Lee”). In reference to claim 1, Lee discloses a structure which meets the claim. Fig. 7A-7D of Lee disclose an epitaxial structure of a semiconductor device which comprises a substrate (41). There is an epitaxial layer (43a, 43b, 44) located on one side of the substrate (41). The epitaxial layer (43a, 43b, 44) comprises at least a first sub-epitaxial layer group (43a, 43a). The first sub-epitaxial layer group (43a, 44) comprises a first sub-epitaxial layer (43a) and a second sub-epitaxial layer (43b) arranged in a stack. The second sub-epitaxial layer (43b) is located on one side of the first sub-epitaxial layer (43a) opposite the substrate (41). A surface of one side of the first sub-epitaxial layer (43a) opposite the substrate (41) comprises a plurality of first dislocation pits (P1). Sidewalls of the first dislocation pits (P1) intersect both a plane where the first sub-epitaxial layer (43a) is located and a first direction which is parallel to a direction in which the first sub-epitaxial layer (43a) points towards the second sub-epitaxial layer (43b). The second sub-epitaxial layer (43b) covers at least the sidewalls of the first dislocation pits (P1). With regard to claim 4, along the first direction, a depth of the first dislocation pit (P1) is h and thickness of the second sub-epitaxial layer (43b) is H2 such that H2>h. In reference to claim 5, the first sub-epitaxial layer (43a) and the second sub-epitaxial layer (43b) both comprise one or more of AlN, GaN, AlGaN, and InGaN (p. 2, paragraph 43). With regard to claim 6, a surface of one side of the first sub-epitaxial layer (43a) opposite the substrate (41) opposite the substrate (41) comprises the first plurality of dislocation pits (P1), with a depth of h, that are formed by corrosive gas etching (p. 4, paragraph 87). The first sub-epitaxial layer (43a) and the second sub-epitaxial layer (43b) can both comprise GaN (p. 2, paragraph 43). The first sub-epitaxial layer (43a) and the second sub-epitaxial layer (43b) can comprise at least one of AlN and AlGaN (p. 2, paragraph 43). Lee does not disclose that the corrosive gas comprises chlorine gas or its specific introduction times (t1, t2) as described by the applicant. However this places the claim into the form of a product-by-process claim: Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Thorpe, 227 USPQ 964, 966; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear. See also MPEP 2113. Claim 6 is not patentable over Lee regardless of the process used to etch the pits, because only the final product is relevant, and not the process of making such as using a chlorine gas and introducing it at t1 or t2 duration times. In reference to claim 7, the epitaxial layer (43a, 43b, 44) further comprises a second sub-epitaxial layer group (43b, 44) located on one side of the first sub-epitaxial layer group (43a, 43b) opposite the substrate (41). The second sub-epitaxial layer group (43b, 44) comprises the second sub-epitaxial layer (43b) and a third sub-epitaxial layer (44). The third sub-epitaxial layer (44) is located on one side of the second sub-epitaxial layer (43b) opposite the substrate (41). A surface of one side of the second sub-epitaxial layer (43b) opposite the substrate (41) comprises a plurality of second dislocation pits (P2). Sidewalls of the second dislocation pits (P2) intersect both a plane where the second sub-epitaxial layer (43b) is located and the first direction. The third sub-epitaxial layer (44) covers at least the sidewalls of the second dislocation pits (P2). In reference to claim 8, Lee discloses a method which meets the claim. Fig. 7A-7D of Lee disclose a method of manufacturing an epitaxial structure of a semiconductor device which comprises providing a substrate (41). A first sub-epitaxial layer group (43a, 43a) is formed on one side of the substrate (41). A first sub-epitaxial layer (43a) is formed on one side of the substrate (41). A plurality of first dislocation pits (P1) are formed on one side of the first sub-epitaxial layer (43a) opposite the substrate (41). Sidewalls of the first dislocation pits (P1) intersect both a plane where the first sub-epitaxial layer (43a) is located and a first direction which is parallel to a direction in which the first sub-epitaxial layer (43a) points towards the second sub-epitaxial layer (43b). The second sub-epitaxial layer (43b) is formed on one side of the first sub-epitaxial layer (43a) opposite the substrate (41). The second sub-epitaxial layer (43b) covers at least the sidewalls of the first dislocation pits (P1). With regard to claim 9, a second sub-epitaxial layer group (43b, 44) is formed on one side of the first sub-epitaxial layer group (43a, 43b) opposite the substrate (41). Forming the second sub-epitaxial layer group (43b, 44) comprises forming a plurality of second dislocation pits (P2) on one side of the second sub-epitaxial layer (43b) opposite the substrate (41). Sidewalls of the second dislocation pits (P2) intersect both a plane where the second sub-epitaxial layer (43b) is located and the first direction. A third sub-epitaxial layer (44) is formed on one side of the second sub-epitaxial layer (43b) opposite the substrate (41). The third sub-epitaxial layer (44) covers at least the sidewalls of the second dislocation pits (P2). The second sub-epitaxial layer group (43b, 44) comprises the second sub-epitaxial layer (43b) and the third sub-epitaxial layer (44). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee. In reference to claim 2, Lee discloses that the first sub-epitaxial layer (43a) has a thickness or H1 from about 150 nm to about 500 nm (p. 4, paragraph 85) while the first dislocation pit depth is less than 1.6 µm or 1600 nm (p. 3, paragraph 51). Claim 2 specifies a range of h such that 1/20H1 ≤ h ≤ 1/2H1. However as noted above, Lee discloses ranges of H1 and ranges of h which overlap and meet the range requirement that 1/20H1 ≤ h ≤ 1/2H1. The examiner would like to note: In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05. Thus claim 2 is not patentable over Lee. With regard to claim 3, Lee discloses that the first sub-epitaxial layer (43a) has a thickness or H1 from about 150 nm to about 500 nm (p. 4, paragraph 85) which is greater than 100 nm. Claim 3 also specifies a range of h such that 5nm ≤ h ≤ 60nm. Lee discloses that the first dislocation pit depth is less than 1.6 µm or 1600 nm (p. 3, paragraph 51) which overlaps the claimed range. The examiner would like to note: In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05. Thus claim 3 is not patentable over Lee. Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kub et al. (United States Patent Application Publication No. US 2014/0264379 A1, hereinafter “Kub”) and further in view of Nguyen et al. (USPN 5,548,140, hereinafter “Nguyen”). In reference to claim 10, Lee discloses the epitaxial structure of claim 1 but does not disclose a semiconductor device such that the epitaxial structure comprises a substrate as well as a nucleation layer, a first sub-epitaxial layer group, a channel layer, a spacer layer, a barrier layer and a cap layer sequentially located on one side of the substrate, a source and a drain located on one side of the barrier layer away from the substrate, and a gate located on one side of the cap layer away from the substrate, the gate being located between the source and the drain. However fig. 1 of Kub discloses a semiconductor device that comprises a substrate as well as a nucleation layer, a first sub-epitaxial layer group (buffer layer), a channel layer, a spacer layer, a barrier layer and a cap layer sequentially located on one side of the substrate, a source and a drain located on one side of the barrier layer away from the substrate, and a gate located on one side of the cap layer away from the substrate with the gate being located between the source and the drain. Nguyen discloses that the buffer layer should filter dislocation defects so that they do not propagate into the subsequently formed layers (column 3, lines 48-50). Lee discloses that the epitaxial structure prevents the propagation of dislocation defects into the subsequently formed layers (p. 1, paragraph 6, p. 3, paragraphs 54 and 62, p. 4-5, paragraph 89). In view of Nguyen and Lee, it would therefore be obvious to implement the epitaxial structure of Lee as the buffer layer in the Kub semiconductor device. Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Choi et al. (United States Patent Application Publication No. US 2013/0248818 A1, hereinafter “Choi”). In reference to claim 11, Lee does not disclose that the hydrogen gas is evacuated from the chamber prior to introducing the corrosive gas to form the plurality of first dislocation pits (P1). However Choi discloses that removing the hydrogen gas from the chamber improves the surface morphology (p. 1, paragraph 15) which is a known goal in the art (p. 1, paragraph 8). In view of Choi, it would therefore be obvious to evacuate the hydrogen gas from the chamber prior to introducing the corrosive gas to form the plurality of first dislocation pits. With regard to claim 12, Lee does not disclose that the hydrogen gas is evacuated from the chamber prior to introducing the corrosive gas to form the plurality of second dislocation pits (P2). However Choi discloses that removing the hydrogen gas from the chamber improves the surface morphology (p. 1, paragraph 15) which is a known goal in the art (p. 1, paragraph 8). In view of Choi, it would therefore be obvious to evacuate the hydrogen gas from the chamber prior to introducing the corrosive gas to form the plurality of second dislocation pits. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 19, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598732
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING MEMORY
2y 5m to grant Granted Apr 07, 2026
Patent 12598730
MEMORY DEVICE AND METHOD FOR FABRICATING SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12581637
METHODS AND STRUCTURES FOR THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY
2y 5m to grant Granted Mar 17, 2026
Patent 12575087
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 10, 2026
Patent 12568613
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
86%
With Interview (+1.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 837 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month