DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Response to Amendment
The amendment filed March 30th, 2026, has been entered. Claims 1-12 are now pending in the application. Applicant’s amendments to the Drawings have overcome each and every objection previously set forth in the Non-Final Office Action mailed December 29th, 2025.
Claim Rejections - 35 USC § 112
Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Applicant recites “wherein an inner surface of the recess is a mirror surface”, and the corresponding subject matter is included in paragraph [0021] of the disclosure. Paragraph [0021] discloses that the inner surface of recess 10 is “changed into a mirror surface by mirror finishing” and that this is done in order suppress thermal contact resistance between mold resin 9 and heat dissipation plate 12. The Merriam-Webster Dictionary defines a mirror as “a polished or smooth surface (as of glass) that forms images by reflection”, and the conventional meaning of “mirror” as understood by someone with ordinary skill in the art similarly hinges on a material’s ability to reflect light. However, it does not appear from the disclosure that applicant intends for the recited surface to reflect light (as would be understood by PHOSITA when applying a broadest reasonable interpretation to the current claim language of claim 9). Therefore, instant claim 9 fails to particular point out and distinctly claim applicant’s invention. Does applicant intend for the term “mirror surface” to convey a degree of smoothness for the recited surface (a “mirror surface” being perhaps smoother than a non-mirror-finished surface)? To overcome this rejection, Examiner suggests that applicant further clarify the precise characteristic of the recited surface. For instance, changing “mirror surface” to “mirror-finished surface” would be an acceptable amendment to overcome this rejection. It should also be noted that the disclosed rational for mirror-finishing the inner surface of the recess (i.e. suppressing thermal contact resistance) could also be accomplished if the inner surface of the recess was made to be smooth. Thus, for the purpose of continued examination, the examiner will construe the claim limitation as wherein an inner surface of the recess is a smooth surface.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1, 4-5, 7, 9-10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hata (US 20120175762 A1), hereinafter referred to as “Hata”, in view of Kaizu et al. (JP 2020064907 A), hereinafter referred to as “Kaizu”;
[Nolan et al. (US 5965267 A), hereinafter referred to as “Nolan”, and Oshima (US 5578894 A), hereinafter referred to as “Oshima”, are utilized herein as evidence].
Regarding claim 1, Hata discloses a semiconductor device (Hata fig. 75, PK12; see [0332]) comprising:
a heat spreader (Hata fig. 75, TAB; see [0329]);
a semiconductor chip (Hata fig. 75, CHP; see [0181]) mounted on the heat spreader;
a frame (Hata fig. 75, CLP; see [0329]) bonded to an upper surface of the semiconductor chip (clip CLP is bonded to semiconductor chip CHP by solder PST3);
mold resin (Hata fig. 75, MR; see [0187]) sealing the heat spreader, the semiconductor chip and the frame and having a recess provided on an upper surface of the mold resin (see Hata fig. 75: heat sink HS is disposed in a recess provided on an upper surface of sealing body MR);
and a heat dissipation plate (Hata fig. 75, HS; see [0330]),
wherein the mold resin is positioned directly between a center of the heat dissipation plate and a center of the semiconductor chip (see Hata fig. 75) such that the heat dissipation plate is insulated and separated from the semiconductor chip and the frame by the mold resin (see Hata fig. 75),
Hata fails to disclose wherein the heat dissipation plate is externally attached to the recess via a thermally conductive material having thermal conductivity higher than that of the mold resin, and wherein the heat dissipation plate is a flat plate having an upper surface and a lower surface which are opposite to each other and flat.
Kaizu discloses a semiconductor device (Kaizu fig. 14, 10) with a heat dissipation plate (Kaizu fig. 14, 24d) disposed in a recess (the recess being defined by uppermost clad material layers 24d and 24e; see annotations above: the inner surface of the recess is the boundary between the recess and the thermally conductive material) on an upper surface of a mold resin body (Kaizu fig. 14, 14) above a semiconductor chip (Kaizu fig. 14, 12), wherein the heat dissipation plate is externally attached to the recess via a thermally conductive material (see Kaizu fig. 14 and [0090]; heat dissipation plate 24d is attached to the recess via alloy layer 24e which contains copper and chromium; since copper and chromium are thermally conductive materials, then alloy layer 24e is a thermally conductive material) having thermal conductivity higher than that of the mold resin (see Kaizu [0025] and [0090]; sealing resin body 14 is formed of epoxy resin, while alloy layer 24e comprises copper and chromium. Under reasonable operating conditions, the thermal conductivity of copper-chromium alloys is higher than the thermal conductivity of epoxy resin (see evidentiary reference Nolan Col. 8, lines 5-8, 12-16: “the thermal conductivity … [is] 401 W/m.K for copper[.] … thermal composite applications add conductive material to an adhesive, such as an epoxy, which has a thermal conductivity of only 0.2 W/m.K”; also see evidentiary reference Oshima fig. 4 which discloses a graph of the thermal conductivities of copper and various copper alloys containing chromium plotted against temperature; note that the thermal conductivities of all of the disclosed materials exceed 150 W/m.K for all temperatures), and wherein the heat dissipation plate is a flat plate having an upper surface and a lower surface which are opposite to each other and flat (see Kaizu fig. 14; see Kaizu [0032]: heat dissipation surface 24b is substantially flush with the back surface 14b of sealing resin body 14; see [0025] and note that the back surface 14b is a flat surface; therefore, given the substantially rectangular shape of layer 24d as shown in fig. 14, layer 24d is a flat plate having an upper surface (24b) and a lower surface which are opposite and flat).
The heat dissipation plate, recess, and thermally conductive material, of Kaizu are incorporated as the heat dissipation plate, recess, and thermally conductive material, in the device of Hata wherein the combination discloses wherein the heat dissipation plate is externally attached to the recess via a thermally conductive material having thermal conductivity higher than that of the mold resin, and wherein the heat dissipation plate is a flat plate having an upper surface and a lower surface which are opposite to each other and flat.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hata with the alloy layer, mold resin, and recess, as taught in Kaizu to reduce the linear expansion coefficient in the lateral direction while preserving heat dissipation functionality (see Kaizu [0093]: “it is possible to reduce the linear expansion coefficient in the direction orthogonal to the Z direction, that is, in the X direction and the Y direction while suppressing the decrease in heat dissipation”).
Regarding claim 4, Hata and Kaizu disclose the semiconductor device according to claim 1, wherein a height of an upper surface of the heat dissipation plate (Kaizu fig. 14, 24d; c.f. Hata fig. 75) is not less than a height of the upper surface of the mold resin (Hata fig. 75, MR; c.f. Kaizu fig. 14; in the combined device, the upper surface of the heat dissipation plate (from Kaizu) is coplanar with the upper surface of the mold resin).
Regarding claim 5, Hata and Kaizu disclose the semiconductor device according to claim 1.
The combined device of Hata and Kaizu fails to disclose wherein a plurality of the recesses and a plurality of the heat dissipation plates are arranged to avoid a trace of an ejector pin or a movable pin on the upper surface of the mold resin.
Kaizu further discloses a semiconductor chip package (Kaizu fig. 2, 10) in a separate embodiment of the disclosed invention. The semiconductor chip package of Kaizu includes a plurality of heat dissipation plates (Kaizu fig. 2, 24H and 24L; see fig. 3 showing a cross-sectional view of heat sinks 24H and 24L in chip package 10) disposed within a plurality of recesses (see Kaizu figs. 2 and 3 and [0033]; fig. 3 shows that heat sinks 24H and 24L are disposed in a plurality of recesses in resin body 14) in mold resin (Kaizu fig. 2, 14), wherein the plurality of the recesses and the plurality of the heat dissipation plates are arranged to avoid a trace of an ejector pin or a movable pin on the upper surface of the mold resin (Kaizu fig. 2, 14b; the plurality of heat sinks 24H and 24L are arranged on a back (i.e. upper) surface 14b of sealing resin body 14; back surface 14b is flat (see Kaizu [0025]) and does not show molding marks such as traces from ejector pins or moveable pins; thus, such marks are avoided in the arrangement of heat sinks 24H and 24L on back surface 14b).
It would have been obvious to modify the previous combined device of Hata and Kaizu with the package arrangement teachings of Kaizu to achieve a substantially rectangular shape for the resin body (see Kaizu [0025]) and to radiate heat from a heat-generating semiconductor chip to the outside of the chip package device (see Kaizu [0030]).
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Regarding claim 7, Hata and Kaizu disclose the semiconductor device according to claim 1, wherein the recess (see Kaizu fig. 14: the recess being defined by uppermost clad material layers 24d and 24e; see annotations of Kaizu fig. 14 provided: the inner surface of the recess is the boundary between the recess and the thermally conductive material; c.f. Hata fig. 75) is arranged immediately above the semiconductor chip (Hata fig. 75, CHP; see [0181]), and a width of the recess is larger than a width of the semiconductor chip (see Hata fig. 75).
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Regarding claim 9, Hata and Kaizu disclose the semiconductor device according to claim 1, wherein an inner surface of the recess is a smooth surface (Applicant is reminded of the above rejection of claim 9 under 35 U.S.C 112(b);
See Kaizu figure 14, [0066], and [0090]; heat sink 24 is comprised of a “clad: material which comprises alternating stacked layers of copper (24d) and a copper alloy material (24e); the topmost copper layer (labeled as 24d in figure 14) is the flat heat dissipation plate, while the topmost alloy layer (labeled as 24e in figure 14) is the thermally conductive adhesive layer; the upper surface of the copper layer below the topmost alloy layer is the inner surface of the recess in which the heat dissipation plate is disposed; according to [0066], the metal laminate structure is formed through a rolling process by which layers are compressed together, so the copper recess surface must be smooth and flat after rolling; it should also be noted that copper has high reflectivity like that of a mirror).
Regarding claim 10, Hata and Kaizu disclose the semiconductor device according to claim 1.
The previously combined device of Hata and Kaizu fails to explicitly disclose wherein the semiconductor chip is made of a wide-band-gap semiconductor.
Kaizu further discloses a semiconductor package (Kaizu fig. 14, 10) comprising a semiconductor chip (Kaizu fig. 14, 12), wherein the semiconductor chip is made of a wide-band-gap semiconductor (see Kaizu [0074] and [0084]: semiconductor chip 12 is made of silicon carbide (SiC)).
The semiconductor chip of Kaizu is incorporated as the semiconductor chip of the combined device of Hata and Kaizu wherein the present combination discloses wherein the semiconductor chip is made of a wide-band-gap semiconductor.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the previously combined device of Hata and Kaizu with the semiconductor chip of Kaizu to achieve higher electron saturation speed than conventional chips (see Kaizu [0074]).
Regarding claim 12, Hata and Kaizu disclose the semiconductor device according to claim 1, wherein there is no insulating plate between the heat dissipation plate (Kaizu fig. 14, 24d; c.f. Hata fig. 75) and the semiconductor chip (Hata fig. 75, CHP; see [0181]; see Hata fig. 75; in the combined device, there is no insulating plate between the heat dissipation plate and the semiconductor chip).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hata, in view of Kaizu, further in view of Otsuka et al. (JP H06232294 A), hereinafter referred to as “Otsuka”
Hata and Kaizu disclose the semiconductor device according to claim 1.
Hata and Kaizu fail to explicitly disclose wherein an excessive amount of the thermally conductive material is accumulated in a gap between a side surface of the recess and a side surface of the heat dissipation plate.
Otsuka discloses a semiconductor device package (Otsuka fig. 1, 1) that includes a heat dissipation plate (Otsuka fig. 1, 8a) attached to a recess (Otsuka fig. 1, 7a) in the upper surface of a mold resin body (Otsuka fig. 1, 7), wherein an excessive amount of the thermally conductive material (see Otsuka fig. 1 and Otsuka page 5, lines 28-30: adhesive layer 9 is silicone rubber containing alumina filler which is thermally conductive) is accumulated in a gap between a side surface of the recess and a side surface of the heat dissipation plate (see Otsuka fig. 1 (annotated above) and Otsuka page 5, lines 13-15; adhesive layer 9 joins convex portion 8a of heat diffusion plate 8 to concave portion 7a (i.e. recess) of package body 7; adhesive material 9 fills the gap between a side surface of package body 7 and a side surface of heat diffusion plate 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Hata and Kaizu with the adhesive interface of Otsuka to enable efficient heat dissipation (see Otsuka page 5, lines 31-34).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hata, in view of Kaizu, further in view of Otsuka, further in view of Tsuji et al. (EP 0484180 A1), hereinafter referred to as “Tsuji”.
Hata, Kaizu, and Otsuka, disclose the semiconductor device according to claim 2.
Hata, Kaizu, and Otsuka, fail to disclose wherein the side surface of the recess is tapered, and the side surface of the heat dissipation plate is a vertical surface.
Tsuji discloses a packaged semiconductor device (see Tsuji fig. 3) having a heat sink structure (Tsuji fig. 3, 10), wherein the side surface of the recess (Tsuji fig. 3, 11; see Col. 6, lines 54-57) is tapered (see Tsuji fig. 3 and Col. 7, lines 8-12; the side surface of resin package body 5 is tapered to form gap 11a), and the side surface of the heat dissipation plate (Tsuji fig. 3, 10) is a vertical surface (see Tsuji fig. 3, the side surface of heat sink 10 adjacent to gap 11a is a vertical surface).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Hata, Kaizu, and Otsuka, with the gap 11a (including the vertical heat sink sidewall and tapered recess sidewall) of Tsuji to allow moisture to escape freely without being trapped at the interface between the mold resin and the heat dissipation plate and thereby prevent the formation of cracks in the mold resin (see Tsuji Col. 7, lines 13-20).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hata, in view of Kaizu, further in view of Lu et al. (US 20130302946 A1), hereinafter referred to as “Lu”.
Hata and Kaizu disclose the semiconductor device according to claim 1.
Hata and Kaizu fail to disclose wherein the frame is provided with a plurality of holes.
Lu discloses a semiconductor package device (see Lu fig. 1, 10), wherein the frame (Lu fig.s 1D, 14; see Lu fig. 2 and [0054]: lead frame 14 is disposed above semiconductor die 20 and includes spaced structures 18 and 19) is provided with a plurality of holes (Lu fig. 1, 108; see Lu fig. 2 and [0060]: throughways 108 are provided in structure 18 of lead frame 14 to allow molding compound 86 to fill void 40 above semiconductor die 20).
The frame throughways of Lu are incorporated into the frame of the combined device of Hata and Kaizu wherein the combination discloses wherein the frame is provided with a plurality of holes.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Hata and Kaizu with the frame throughways of Lu to enable the mold resin to better lock on to the frame (see Lu [0060]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hata, in view of Kaizu, further in view of Michii et al. (US 20020173076 A1), hereinafter referred to as “Michii”.
Hata and Kaizu disclose the semiconductor device according to claim 1.
Hata and Kaizu fail to explicitly disclose wherein a thickness of the mold resin above the frame is 0.2 mm to 1.0 mm.
Michii discloses a multi-chip semiconductor package (see Michii fig. 1) with a lead frame (Michii fig. 1, 14) bonded to an upper surface of a semiconductor chip (Michii fig. 1, 10), wherein a thickness of the mold resin (Michii fig. 1, 17) above the frame is 0.2 mm to 1.0 mm (see Michii fig.s 1 and 4, [0021], and [0105]-[0106]; [0021] states that a lead frame includes inner lead 14 and outer lead 19; figs. 1 and 4 show that dimension D extends from the top of inner lead 14 to the top end portion of metallic wire 16a, and [0106] confirms that dimension D is 0.09 mm. [0106] further discloses that “[a] top end portion of the metallic wire is sealed by a sealing resin 17 having a thickness of 0.136 mm”; therefore, the thickness of mold resin 17 above inner lead 14 is 0.09 + 0.136 = 0.226 mm which is within the claimed range).
The thickness of the mold resin above the frame in the device of Michii is incorporated as the thickness of the mold resin between the frame and the heat dissipation plate in the combined device of Hata and Kaizu wherein the combination discloses wherein a thickness of the mold resin above the frame is 0.2 mm to 1.0 mm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Hata and Kaizu with the mold resin thickness teachings of Michii to reduce the thickness of the semiconductor device and achieve a thin device (see Michii [0017] and [0106]; it is clear that one of the aims of Michii is to provide a thin semiconductor device and specifically a device with a thickness of 1 mm or less; it should also be noted that the benefit of thinner device designs is well known in the art).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hata, in view of Kaizu, further in view of Kato et al. (JP 2019192877 A), hereinafter referred to as “Kato”.
Hata and Kaizu disclose the semiconductor device according to claim 1.
Hata and Kaizu fail to disclose an inverter unit comprising: the semiconductor device according to claim 1; and a cooler arranged on an upper surface side and an lower surface side of the semiconductor device, wherein the heat spreader and the heat dissipation plate are thermally connected to the cooler without via an insulating substrate.
Kato discloses an inverter unit (see Kato [0038]) comprising: a semiconductor device (Kato fig. 6, 100); and a cooler (see Kato [0038]: “cooling device”) arranged on an upper surface side (see Kato [0038] and fig. 6; “the semiconductor device 100 is attached to a cooling device (not shown), for example, to release the heat, and the exposed surfaces of the heat sinks 22 and 32 are exposed to the refrigerant in the cooling device”; the upper surface side of semiconductor device 100 includes the exposed surface of heat sink 32, and a cooler is arranged on the upper surface side such that heat sink 32 is exposed to the refrigerant in the cooler) and an lower surface side (see Kato [0038] and fig. 6; the lower surface side of semiconductor device 100 includes the exposed surface of heat sink 22, and a cooler is arranged on the lower surface side such that heat sink 22 is exposed to the refrigerant in the cooler) of the semiconductor device, wherein the heat spreader (Kato fig. 6, 22) and the heat dissipation plate (Kato fig. 6, 32) are thermally connected to the cooler without via an insulating substrate (see Kato fig. 6 and [0038]; heat sinks 22 and 32 of semiconductor device 100 are both in contact with the refrigerant in the enveloping cooler).
The combined device of Hata and Kaizu is incorporated into the inverter unit of Kato wherein the combination discloses an inverter unit comprising: the semiconductor device according to claim 1; and a cooler arranged on an upper surface side and an lower surface side of the semiconductor device, wherein the heat spreader and the heat dissipation plate are thermally connected to the cooler without via an insulating substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to integrate the combined device of Hata and Kaizu into the inverter unit of Kato to create an inverter component for an automobile utilizing the previously combined device.
Response to Arguments
Applicant’s arguments filed March 30th, 2026, have been fully considered, the majority of said arguments being unpersuasive.
On page 6 of applicant’s response, applicant suggests that the previous rejection of claim 9 under 35 U.S.C. 112(b) is improper because there is nothing unclear about the recitation “mirror surface” since PHOSITA would fully understand the scope of a mirror surface. Upon further consideration, Examiner finds the basis of this suggestion unpersuasive. While PHOSITA would fully understand the scope of “mirror surface”, they would not understand the scope of the term when applied to the instant invention (since “mirror surface” is generally construed in the art to imply a surface that reflects light). Therefore, the claim language fails to particularly point out and distinctly claim the intended invention, and the 112(b) rejection of claim 9 is maintained. In the 112(b) rejection given above, examiner has attempted to clarify the Office’s position and provide suggestions for how applicant might amend the claim language to overcome the rejection during future stages of prosecution.
On page 7 of applicant’s response, applicant suggests that the cited references, taken alone or in combination, fail to disclose, suggest, or otherwise render obvious the limitation in amended claim 1 reciting the mold resin being centered between the thermally conductive material and the semiconductor chip such that the heat dissipation plate is insulated and separated from the semiconductor chip. In support of this suggestion, Applicant further alleges that (1) Kato fails to include any mold resin 60 between a center of heat sink 32 and a center of semiconductor chip 10 (see Kato fig. 6) and (2) Kaizu fails to disclose that the Cu layer 24d is insulated from semiconductor chip 12 (see Kaizu fig. 14). Examiner agrees with allegation (1); Kato fails to disclose mold resin 60 being centered between heat sink 32 and semiconductor chip 10. The teachings of Hata as relied upon in the updated 103 rejection of amended claim 1 remedy this deficiency. Examiner respectfully disagrees with allegation (2); using the broadest reasonable interpretation, it can be seen that portions of Cu layer 24d (on either side of terminal 20) are insulated from semiconductor chip 12 by portions of resin body 14 (even if layer 24d is not completely insulated from semiconductor chip 12). Regardless, the updated 103 rejection of amended claim 1 relying upon the teachings of Hata renders these issues moot since the combined device of Hata and Kaizu discloses all of the limitations recited in said claim. Therefore, the 103 rejection of amended claim 1 is maintained.
On page 7 of applicant’s response, applicant suggests that new claim 12 is allowable. Examiner respectfully disagrees; please see the 103 rejection of claim 12 entered above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571)272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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