DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “gap 14” as described in the paragraph [0023] of the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Applicant recites “wherein an inner surface of the recess is a mirror surface”, and the corresponding subject matter is included in paragraph [0021] of the disclosure. However, it is unclear what exactly is meant by “mirror surface”: how exactly can the mold resin, a plastic (epoxy) with a low reflectivity, be changed to reflect light similar to a mirror? Is it instead intended that the inner surface of the recess be a smooth surface to reduce the thermal contact resistance between the mold resin and the heat dissipation plate? To overcome this rejection, applicant should clarify the precise meaning of “mirror surface”. For the purpose of examination, the examiner will construe the claim limitation as wherein an inner surface of the recess is a smooth surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (JP 2019192877 A), hereinafter referred to as “Kato”, in view of Kaizu et al. (JP 2020064907 A), hereinafter referred to as “Kaizu”;
[Nolan et al. (US 5965267 A), hereinafter referred to as “Nolan”, and Oshima (US 5578894 A), hereinafter referred to as “Oshima”, are utilized herein as evidence].
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Regarding claim 1, Kato discloses a semiconductor device (Kato figure 6, 100) comprising: a heat spreader (Kato figure 6, 22) ; a semiconductor chip (Kato figure 6, 10) mounted on the heat spreader; a frame (Kato figure 6, 31a; see [0034]: “the second external lead 72 is integrally or electrically connected to the first metal plate 31a”) bonded to an upper surface of the semiconductor chip; mold resin (Kato figure 6, 60) sealing the heat spreader, the semiconductor chip and the frame (see Kato figure 6 and [0019]: the mold resin 60 seals the heat sink 22 (included in first heat dissipation structure 20), semiconductor chip 10, and first metal plate 31a) and having a recess (see Kato figure 6: upper heat sink 32 is provided in a recess in the upper surface of mold resin 60) provided on an upper surface of the mold resin; and a heat dissipation plate (Kato figure 6, 32), wherein the heat dissipation plate is insulated from the semiconductor chip and the frame by the mold resin (see Kato figure 6: heat sink 32 is insulated from the frame (comprising first metal plate 31a and second external lead 72) and semiconductor chip 10 by the portion of mold resin 60 disposed therebetween (i.e. the portion of mold resin laterally adjacent to second metal plate 31b)), and wherein the heat dissipation plate is a flat plate (see Kato figure 6 and [0054]: heat sink 32 is a plate-like member with flat surfaces) having an upper surface (see Kato figure 6: the surface of heat sink 32 facing away from semiconductor chip 10) and a lower surface (see Kato figure 6: the surface of heat sink 32 facing toward the semiconductor chip 10) which are opposite to each other (the upper and lower surfaces of heat sink 32 are opposite each other) and flat (see Kato figure 6 and [0054]).
Kato does not disclose wherein the heat dissipation plate is externally attached to the recess via a thermally conductive material having thermal conductivity higher than that of the mold resin.
Kaizu discloses a semiconductor device (Kaizu figure 14, 10) with a heat dissipation plate (Kaizu figure 14, 24d) disposed in a recess (the recess being defined by uppermost clad material layers 24d and 24e; see annotations above: the inner surface of the recess is the boundary between the recess and the thermally conductive material) on an upper surface of a mold resin body (Kaizu figure 14, 14) above a semiconductor chip (Kaizu figure 14, 12), wherein the heat dissipation plate is externally attached to the recess via a thermally conductive material (see Kaizu figure 14 and [0090]; heat dissipation plate 24d is attached to the recess via alloy layer 24e which contains copper and chromium; since copper and chromium are thermally conductive materials, then alloy layer 24e is a thermally conductive material) having thermal conductivity higher than that of the mold resin (see Kaizu [0025] and [0090]; sealing resin body 14 is formed of epoxy resin, while alloy layer 24e comprises copper and chromium. Under most operating conditions, the thermal conductivity of copper-chromium alloys is higher than the thermal conductivity of epoxy resin (see evidentiary reference Nolan Col. 8, lines 5-8, 12-16: “the thermal conductivity … [is] 401 W/m.K for copper[.] … thermal composite applications add conductive material to an adhesive, such as an epoxy, which has a thermal conductivity of only 0.2 W/m.K”;
also see evidentiary reference Oshima figure 4 which discloses a graph of the thermal conductivities of copper and various copper alloys containing chromium plotted against temperature; note that the thermal conductivities of all of the disclosed materials exceed 150 W/m.K for all temperatures).
The alloy layer and mold resin of Kaizu is incorporated as the bonding material and mold resin of the semiconductor device taught in Kato (see Kato figure 6: bonding material 50e and mold resin 60), wherein the heat dissipation plate (Kato figure 6, 32) is externally attached to the recess via a thermally conductive material (Kaizu figure 14, 24e) having thermal conductivity higher than that of the mold resin.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kato with the alloy layer and mold resin as taught in Kaizu to reduce the linear expansion coefficient in the lateral direction while preserving heat dissipation functionality (see Kaizu [0093]: “it is possible to reduce the linear expansion coefficient in the direction orthogonal to the Z direction, that is, in the X direction and the Y direction while suppressing the decrease in heat dissipation”); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the alloy layer and mold resin of Kaizu (Kaizu figure 14, 24e and 14 respectively) with the bonding material and mold resin in the device of Kato (Kato figure 6, 50e and 60 respectively) to obtain predicable results (see Kaizu [0093]).
Regarding claim 4, Kato and Kaizu disclose the semiconductor device according to claim 1, wherein a height of an upper surface of the heat dissipation plate is not less than a height of the upper surface of the mold resin (see Kato figure 6: the upper surface of heat sink 32 is level with the upper surface of mold resin 60).
Regarding claim 5, Kato and Kaizu disclose the semiconductor device according to claim 1.
However, the combined device of Kato and Kaizu does not include wherein a plurality of the recesses and a plurality of the heat dissipation plates are arranged to avoid a trace of an ejector pin or a movable pin on the upper surface of the mold resin.
Kaizu further discloses a semiconductor chip package (Kaizu figure 2, 10) in a separate embodiment of the disclosed invention. The semiconductor chip package of Kaizu includes a plurality of heat dissipation plates (Kaizu figure 2, 24H and 24L; see figure 3 showing a cross-sectional view of heat sinks 24H and 24L in chip package 10) disposed within a plurality of recesses (see Kaizu figures 2 and 3 and [0033]; figure 3 shows that heat sinks 24H and 24L are disposed in a plurality of recesses in resin body 14) in mold resin (Kaizu figure 2, 14), wherein the plurality of the recesses and the plurality of the heat dissipation plates are arranged to avoid a trace of an ejector pin or a movable pin on the upper surface of the mold resin (Kaizu figure 2, 14b; the plurality of heat sinks 24H and 24L are arranged on a back (i.e. upper) surface 14b of sealing resin body 14; back surface 14b is flat (see Kaizu [0025]) and does not show molding marks such as traces from ejector pins or moveable pins; thus, such marks are avoided in the arrangement of heat sinks 24H and 24L on back surface 14b).
It would have been obvious to modify the combined device of Kato and Kaizu with the chip package teachings of Kaizu to achieve a substantially rectangular shape for the resin body (see Kaizu [0025]) and to radiate heat from a heat-generating semiconductor chip to the outside of the chip package device (see Kaizu [0030]).
Regarding claim 7, Kato and Kaizu disclose the semiconductor device according to claim 1, wherein the recess is arranged immediately above the semiconductor chip, and a width of the recess is larger than a width of the semiconductor chip (see Kato figure 6; the widths of heat sink 32 and the recess in which it is placed are both larger than the width of semiconductor chip 10).
Regarding claim 9, Kato and Kaizu disclose the semiconductor device according to claim 1, wherein an inner surface of the recess is a smooth surface (Applicant is reminded of the above rejection of claim 9 under 35 U.S.C 112(b); examiner will construe the claim limitation as reciting a surface of the mold resin recess that is smooth;
See Kaizu figure 14, [0066], and [0090]; heat sink 24 is comprised of a “clad: material which comprises alternating stacked layers of copper (24d) and a copper alloy material (24e); the topmost copper layer (labeled as 24d in figure 14) is the flat heat dissipation plate, while the topmost alloy layer (labeled as 24e in figure 14) is the thermally conductive adhesive layer; the upper surface of the copper layer below the topmost alloy layer is the inner surface of the recess in which the heat dissipation plate is disposed; according to [0066], the metal laminate structure is formed through a rolling process by which layers are compressed together, so the copper recess surface must be smooth and flat after rolling; it should also be noted that copper has high reflectivity like that of a mirror).
Regarding claim 10, Kato and Kaizu disclose the semiconductor device according to claim 1, wherein the semiconductor chip is made of a wide-band-gap semiconductor (see Kato [0023]; semiconductor chip 10 is composed of gallium nitride (GaN) which is a wide-band-gap semiconductor material).
Regarding claim 11, Kato and Kaizu disclose an inverter unit (see Kato [0038]; the semiconductor device 100 of Kato can be incorporated into an inverter unit) comprising: the semiconductor device according to claim 1; and a cooler (see Kato [0038]: “cooling device”) arranged on an upper surface side (see Kato [0038] and figure 6; “the semiconductor device 100 is attached to a cooling device (not shown), for example, to release the heat, and the exposed surfaces of the heat sinks 22 and 32 are exposed to the refrigerant in the cooling device”; the upper surface side of semiconductor device 100 includes the exposed surface of heat sink 32, and a cooler is arranged on the upper surface side such that heat sink 32 is exposed to the refrigerant in the cooler) and an lower surface side (see Kato [0038] and figure 6; the lower surface side of semiconductor device 100 includes the exposed surface of heat sink 22, and a cooler is arranged on the lower surface side such that heat sink 22 is exposed to the refrigerant in the cooler) of the semiconductor device, wherein the heat spreader (Kato figure 6, 22) and the heat dissipation plate (Kato figure 6, 32) are thermally connected to the cooler without via an insulating substrate (see Kato figure 6 and [0038]; heat sinks 22 and 32 of semiconductor device 100 are both in contact with the refrigerant in the enveloping cooler, so an insulating substrate is not used).
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Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, in view of Kaizu, further in view of Otsuka et al. (JP H06232294 A), hereinafter referred to as “Otsuka”.
Kato and Kaizu disclose the semiconductor device according to claim 1.
Kato and Kaizu do not disclose wherein an excessive amount of the thermally conductive material is accumulated in a gap between a side surface of the recess and a side surface of the heat dissipation plate.
Otsuka discloses a semiconductor device package (Otsuka figure 1, 1) that includes a heat dissipation plate (Otsuka figure 1, 8a) attached to a recess (Otsuka figure 1, 7a) in the upper surface of a mold resin body (Otsuka figure 1, 7), wherein an excessive amount of the thermally conductive material (see Otsuka figure 1 and Otsuka page 5, lines 28-30: adhesive layer 9 is silicone rubber containing alumina filler which is thermally conductive) is accumulated in a gap between a side surface of the recess and a side surface of the heat dissipation plate (see Otsuka figure 1 (annotated above) and Otsuka page 5, lines 13-15; adhesive layer 9 joins convex portion 8a of heat diffusion plate 8 to concave portion 7a (i.e. recess) of package body 7; adhesive material 9 fills the gap between a side surface of package body 7 and a side surface of heat diffusion plate 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kato and Kaizu with the adhesive interface of the device taught in Otsuka to enable efficient heat dissipation (see Otsuka page 5, lines 31-34).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, in view of Kaizu, in view of Otsuka, further in view of Tsuji et al. (EP 0484180 A1), hereinafter referred to as “Tsuji”.
Kato, Kaizu, and Otsuka, disclose the semiconductor device according to claim 2.
Kato, Kaizu, and Otsuka, do not disclose wherein the side surface of the recess is tapered, and the side surface of the heat dissipation plate is a vertical surface.
Tsuji discloses a packaged semiconductor device (see Tsuji figure 3) having a heat sink structure (Tsuji figure 3, 10), wherein the side surface of the recess (Tsuji figure 3, 11; see Col. 6, lines 54-57) is tapered (see Tsuji figure 3 and Col. 7, lines 8-12; the side surface of resin package body 5 is tapered to form gap 11a), and the side surface of the heat dissipation plate (Tsuji figure 3, 10) is a vertical surface (see Tsuji figure 3, the side surface of heat sink 10 adjacent to gap 11a is a vertical surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kato, Kaizu, and Otsuka, with the gap 11a (including the vertical heat sink sidewall and tapered recess sidewall) of Tsuji to allow moisture to escape freely without being trapped at the interface between the mold resin and the heat dissipation plate and thereby prevent the formation of cracks in the mold resin (see Tsuji Col. 7, lines 13-20).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, in view of Kaizu, further in view of Lu et al. (US 20130302946 A1), hereinafter referred to as “Lu”.
Kato and Kaizu disclose the semiconductor device according to claim 1.
Kato and Kaizu do not disclose wherein the frame is provided with a plurality of holes.
Lu discloses a semiconductor package device (see Lu figure 1, 10), wherein the frame (Lu figures 1D, 14; see Lu figure 2 and [0054]: lead frame 14 is disposed above semiconductor die 20 and includes spaced structures 18 and 19) is provided with a plurality of holes (Lu figure 1, 108; see Lu figure 2 and [0060]: throughways 108 are provided in structure 18 of lead frame 14 to allow molding compound 86 to fill void 40 above semiconductor die 20).
The frame throughways of Lu are incorporated into the frame of the combined device of Kato and Kaizu.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kato and Kaizu with the frame throughways of Lu to help mold resin lock on to the frame (see Lu [0060]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, in view of Kaizu, further in view of Michii et al. (US 20020173076 A1), hereinafter referred to as “Michii”.
Kato and Kaizu disclose the semiconductor device according to claim 1.
Kato and Kaizu do not disclose wherein a thickness of the mold resin above the frame is 0.2 mm to 1.0 mm.
Michii discloses a multi-chip semiconductor package (see Michii figure 1) with a lead frame (Michii figure 1, 14) bonded to an upper surface of a semiconductor chip (Michii figure 1, 10), wherein a thickness of the mold resin (Michii figure 1, 17) above the frame is 0.2 mm to 1.0 mm (see Michii figures 1 and 4, [0021], and [0105]-[0106]; [0021] states that a lead frame includes inner lead 14 and outer lead 19; figures 1 and 4 show that dimension D extends from the top of inner lead 14 to the top end portion of metallic wire 16a, and [0106] confirms that dimension D is 0.09 mm. [0106] further discloses that “[a] top end portion of the metallic wire is sealed by a sealing resin 17 having a thickness of 0.136 mm”; therefore, the thickness of mold resin 17 above inner lead 14 is 0.09 + 0.136 = 0.226 mm which is within the claimed range).
The thickness of the mold resin above the frame in the device of Michii is incorporated as the thickness of the mold resin between the frame and the heat dissipation plate in the combined device of Kato and Kaizu.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Kato and Kaizu with the mold resin thickness teachings of Michii to reduce the thickness of the semiconductor device and achieve a thin device (see Michii [0017] and [0106]; it is clear that one of the aims of Michii is to provide a thin semiconductor device and specifically a device with a thickness of 1 mm or less; it should also be noted that the benefit of thinner device designs is well known in the art); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the mold resin thickness above the frame in the combined device of Kato and Kaizu (see Kato figure 6: heat sink 32 is insulated from the frame (comprising first metal plate 31a and second external lead 72) and semiconductor chip 10 by the portion of mold resin 60 disposed therebetween (i.e. the portion of mold resin laterally adjacent to second metal plate 31b)) with the mold resin thickness above the frame as taught in Michii (see Michii figures 1 and 4, [0021], and [0105]-[0106]) to obtain predicable results (see Michii [0017] and [0106]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/SAMUEL PARK/
Primary Examiner, Art Unit 2818