Prosecution Insights
Last updated: May 29, 2026
Application No. 18/551,648

PHOTODETECTION DEVICE AND ELECTRONIC DEVICE

Non-Final OA §112
Filed
Sep 21, 2023
Priority
Mar 31, 2021 — JP 2021-062383 +1 more
Examiner
JEAN BAPTISTE, WILNER
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
932 granted / 1079 resolved
+18.4% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1110
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
81.0%
+41.0% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1079 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 2. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. 4. The claims recite in multiple locations “an optical element" and "an optical system". Claims 1-8, 10-19 are to a photodetection device, while claims 9 and 20 refer to an electronic device, and from the disclosure it is unclear what structural differences if any are implied by the claimed language. Thus, the use of said language may invite confusion as to the scope of the claims. Where possible, the Examiner will interpret the limitations as being drawn to the intended use of the lines to carry “an optical element" and "an optical system". As noted, optical elements are the fundamental building blocks of optical systems. They influence light (often in the form of light beams) in controlled ways to manipulate its propagation, direction, optical intensity, or spectral composition. While specific types of optical elements are explained in depth in separate Encyclopedia articles, here we give an overview. For example, an optical element is a single component (like a lens, mirror, or filter) that manipulates light, while an optical system is a collection of these individual elements arranged together to perform a more complex function, such as creating an image in a camera or telescope, with the system's overall performance depending on the interaction between all its parts. Think of elements as building blocks and the system as the final structure built from them. If Applicant wishes to persist with this language, it is recommended Applicant claim structural features which may distinguish the key difference. If Applicant feels a telephone conversation would expedite this matter, the Examiner can be reached at the number below. Allowable Subject Matter 5. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Remarks: 6. The closest prior art is Lee, US 2019/0348453 A1. However, Lee does not teach or suggest a plurality of first connecting elements disposed on the plurality of connecting pads, respectively; and a substrate comprising a plurality of second connecting elements disposed on a mounting surface of the substrate, wherein the plurality of first connecting elements are electrically connected to the plurality of second connecting elements through an anisotropic conductive structure, wherein the anisotropic conductive structure is disposed between the plurality of first connecting elements and the plurality of second connecting elements, as in the claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 21, 2023
Application Filed
Jan 27, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642139
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
3y 1m to grant Granted May 26, 2026
Patent 12629782
WAFER PROCESSING METHOD
2y 4m to grant Granted May 19, 2026
Patent 12628662
SEMICONDUCTOR CHIP, CHIP SYSTEM, METHOD OF FORMING A SEMICONDUCTOR CHIP, AND METHOD OF FORMING A CHIP SYSTEM
3y 4m to grant Granted May 12, 2026
Patent 12628687
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted May 12, 2026
Patent 12628430
3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS
11m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
92%
With Interview (+5.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1079 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month