DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
Present application 18/551,802 filed 09/21/2023 is a National Stage entry of PCT/EP2022/055100 with international filing date of 03/01/2022.
Foreign Priority
Receipt is acknowledged of certified copies of papers (i.e., application number 10 2021 108 756.2 filed in Germany on 04/08/2021) required by 37 CFR 1.55, received on 09/21/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/21/2023 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title or similar is suggested:
-- METHOD FOR ELECTRICAL TESTING A WAFER INCLUDING A LOCAL ANNEALING AND WAFER THEREOF --.
A. Broadest reasonable interpretation prior art rejection with primary reference Slater
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17, 27 and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0104072 A1 to Slater, JR et al. (“Slater”).
Regarding independent claim 17, Slater teaches of a method for performing a functional test (as defined/described below) on a wafer 100/105 (“epitaxial layer”/”SiC substrate”; Figures 1, 8; paragraph 0056), the method comprising:
providing the wafer 100/105 with a semiconductor layer 105 (this may be considered a layer because in a certain orientation as per Figure 1 it sits atop 100) sequence arranged on a substrate 100 (this may be considered a substrate because in a certain orientation as per Figures 1, 8 it is below 105);
attaching at least one first contact element 940a-d (“metal layer”; Figure 9; paragraph 0064) to a main surface (i.e., this is the main surface of 105 because this is the location of 940 of interest) of the semiconductor layer 105 sequence facing away from the substrate 100;
attaching at least one second contact 940a-d (another of 940a-d the “metal layer”; Figure 9; paragraph 0064) element to the main surface (i.e., this is the main surface of 105 because this is the location of 940 of interest) of the semiconductor layer 105 sequence at a distance (i.e., difference in locations of 940s) to the first contact element (i.e., 940s); and
applying a first electrical potential to the first contact element and a second electrical potential to a second contact element, wherein the first electrical potential and the second electrical potential are different from each other (Basis in fact: the ohmic contacts enable application of electrical potentials for device operation. For instance, the Background section teaches of applying voltage to achieve low forward voltage of about 3.5 volts at 10mA. Electrical characterization is implied for verifying contact resistivity –see paragraph 0053, which involves applying differing potentials to measure current flow. In other words, definitions of low resistivity contacts support current flow under applied bias. There does appear to be electrical characterization post formation of the contacts),
wherein, by locally annealing (see paragraphs 0029-0030, 0060) the semiconductor layer sequence 105, a first contact region (i.e., metal-SiC) is formed in a region of the first contact element 940a-d and a second contact region (i.e., metal-SiC), which is spaced apart from the first contact region (i.e., metal-SiC), is formed in a region of the second contact element 940a-d.
Regarding independent claim 27, Slater teaches wherein the second contact element 940a-d is formed simultaneously (see Figure 8 to Figure 9; formed in the same process at same time) with the first contact element 940a-d by the same process.
Regarding device independent claim 34 that is directed towards “a wafer.” This is a device that is being defined in terms of: product-by-process with respect to the limitations requiring a locally elevated temperature; and also in terms of its method-of-use in terms of the limitations requiring certain applied potentials. In both cases, the structure implied is that which is already taught by Slater in claim 1 rejection supra. The structure implied by the locally elevated temperatures is that of the locations of the contacts 940 and the structure implied by the applied potentials is taught by the locations of the contacts 940.
B. Prior art rejection with primary reference Tu.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0203282 A1 to Tu et al. (“Tu”).
Regarding independent claim 17, Tu teaches of a method for performing a functional test on a wafer (see title), the method comprising:
providing the wafer (see Figures 1-2 and paragraph 0021) with a semiconductor layer sequence (i.e., epitaxial layer, 210) arranged on a substrate (see paragraph 0021; bulk semiconductor);
attaching at least one first contact element 290 (“plugs”; Figure 1; see paragraph 0033) to a main surface (i.e., device side of epitaxial layer 210) of the semiconductor layer sequence 210 facing away from the substrate (i.e., bulk semiconductor);
attaching at least one second contact element (i.e., another 290) to the main surface (i.e., device side of epitaxial layer 210) of the semiconductor layer sequence 210 at a distance (i.e., different 290s) to the first contact element 290; and
applying a first electrical potential to the first contact element 290 and a second electrical potential to a second contact element 290, wherein the first electrical potential and the second electrical potential are different from each other (see Figures 1-3; paragraph 0041; different electrical potentials are applied to contacts 290),
wherein, by locally annealing (paragraph 0029; the source/drain regions 250 are annealed by laser annealing which necessarily implies local annealing because of irradiation with laser in specific location. The annealed regions of the source/drain regions 250 touch contacts 290 are the claimed contact regions) the semiconductor layer sequence 210, a first contact region (i.e., source/drain region) is formed in a region of the first contact element 290 and a second contact region (i.e., drain/source region), which is spaced apart from the first contact region (i.e., source/drain region), is formed in a region of the second contact element 290.
Regarding device independent claim 34 that is directed towards “a wafer.” This is a device that is being defined in terms of: product-by-process with respect to the limitations requiring a locally elevated temperature; and also in terms of its method-of-use in terms of the limitations requiring certain applied potentials. In both cases, the structure implied is that which is already taught by Tu in claim 1 rejection supra. The structure implied by the locally elevated temperatures is that of the locations of the contacts 290 and the structure implied by the applied potentials is taught by the locations of the contacts 290 also.
C. Prior art rejection with primary reference Edelstein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 18, 19, 28, 33 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over US 7,098,050 B1 to Edelstein et al. (“Edelstein”) in view of US 2005/0104072 A1 to Slater, JR et al. (“Slater”).
Regarding independent claim 17, Edelstein teaches of a method for performing a functional test (see Figure 1 and Edelstein’s claim 1; measuring system 10 measures gate structures on a wafer) on a wafer (see Edelstein’s claim 18: the substrate may include epitaxial silicon), the method comprising:
providing the wafer (i.e., as per above: this may be epitaxial silicon and whatever the epitaxial silicon is grown on) with a semiconductor layer (i.e., epitaxial silicon = 30 of Figure 3 along with gate layer 26) sequence arranged on a substrate (i.e., bulk semiconductor);
attaching at least one first contact element (see Figure 3; application of electrode 28) to a main surface (i.e., device side of 30) of the semiconductor layer 30+26 sequence facing away from the substrate (i.e., bulk semiconductor);
attaching at least one second contact element (see Figure 3; column 5, lines 9-19; Kelvin electrodes for the source/drain regions 32) to the main surface (i.e., device side of 30) of the semiconductor layer 30 sequence at a distance to the first contact element 28; and
applying a first electrical potential to the first contact element 28 and a second electrical potential to a second contact element (i.e., Kelvin electrodes), wherein the first electrical potential and the second electrical potential are different from each other (see Figure 3; column 5, lines 1-19),
wherein, by locally annealing (see Figure 2; column 4, lines 9-68; gate layer 26 is locally annealed by laser annealing; this necessarily takes place in the region of the electrode 28) the semiconductor layer sequence 30+26, a first contact region 26 is formed in a region of the first contact element 28;
The problem encountered by Edelstein as suggested by Slater is that of improved resistivity of an ohmic contact between semiconductor and electrode/contact.
Slater solves this issue by local annealing as per paragraphs 0028, 0060 in order to improve resistivity as per paragraph 0053.
As such Slater makes obvious local annealing the location of the Kelvin electrodes of Edelstein for improved contact.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Slater’s local annealing of contacts with the Edelstein’s invention would have been beneficial as best suggested by Slater in paragraphs 0053,0060 for improved resistivity in contact-semiconductor areas.
Regarding claim 18, Edelstein teaches wherein the semiconductor layer sequence 26 is annealed before (see Figure 4) the first contact element 28 is attached, wherein annealing is carried out at least in a region at the main surface (i.e., device side) where the first contact element 28 is subsequently attached.
Regarding claim 19, Edelstein teaches wherein the semiconductor layer sequence 26 is locally annealed (see Figure 4) in a region of the first contact element 28.
Regarding claim 28, Slater makes obvious wherein the semiconductor layer sequence 105 is locally annealed by radiation of a first wavelength range (see paragraph 0060: there is laser annealing in specific locations),
wherein the radiation of the first wavelength range is absorbed by at least a part of the first contact element 735a-d (i.e., absorbed because there is metal-SiC created), and
wherein an average temperature of the semiconductor layer sequence 105 in the first contact region 735a-d during annealing is at least 50° C (given the local annealing as per paragraph 0060 and given lower temperatures than that discussed in paragraph 0006; therefore it appears that the range of temperatures used by Slater overlaps the claimed range) higher than an average temperature of the semiconductor layer sequence outside (i.e., due to local annealing as per paragraph 0060) the first contact region 735a-d.
Regarding claim 33, Slater makes obvious use of photolithography for positions of the claimed contact elements as mentioned in paragraph 0071.
Regarding device independent claim 34 that is directed towards “a wafer.” This is a device that is being defined in terms of: product-by-process with respect to the limitations requiring a locally elevated temperature; and also in terms of its method-of-use in terms of the limitations requiring certain applied potentials. In both cases, the structure implied is that which is already taught by Edelstein in view of Slater in claim 1 rejection supra. The structure implied by the locally elevated temperatures is that of the locations of the contacts and the structure implied by the applied potentials is taught by the locations of the contacts.
Allowable Subject Matter
Claims 20-26 and 29-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 20, wherein a contact layer is applied to the main surface before annealing, wherein the first contact element is applied in places to the contact layer, wherein a protective layer followed by a mask layer is applied on a side of the contact layer facing away from the semiconductor layer sequence, wherein the mask layer is patterned thereby forming openings in the mask layer so that the contact element is not covered by the mask layer in view of the main surface and so that the protective layer is exposed in the openings, wherein the protective layer is removed in regions of the openings so that the contact layer and the first contact element are exposed, wherein the contact layer is removed in regions of the openings, which are free of the first contact element in view of the main surface, and wherein the mask layer is completely removed.
The combination of references listed in the IDS would be impermissible hindsight as applied to the limitations of claim 20 when combined with Slater, Tu or Edelstein.
Dependent claims 21-26 contain allowable subject matter, because they depend on the allowable subject matter of claims 21-26.
Claim 29 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 29, wherein a first wavelength range is selected such that the semiconductor layer sequence is transparent for radiation of the first wavelength range.
Claim 30 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 30, wherein the main surface is irradiated with the radiation of the first wavelength range from a direction of a side of the semiconductor layer sequence facing away from the contact elements.
Claim 31 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 31, wherein an intermediate layer is formed between the first contact element and the semiconductor layer sequence, wherein material for the intermediate layer is applied as a contact layer flat on the main surface of the semiconductor layer sequence, wherein the first contact element is applied in places to the contact layer, and wherein the contact layer is removed in regions that are free of the first contact element in view of the main surface.
Claim 32 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 32, wherein all contact elements are removed in a further method step.
The prior art of Edelstein removes only the Kelvin electrodes and not the electrode 28.
Conclusion
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03 January 2026
/John P. Dulka/Primary Examiner, Art Unit 2817