DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20090134430 (Abe et al).
Concerning claim 1, Abe discloses a semiconductor device comprising multiple transistors coupled in parallel to each other ([0091]),
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wherein each of the transistors includes a gate electrode (31), a source electrode, and a drain electrode that extend in a first direction ([0091]), a plurality of the gate electrodes provided one by one to each of the transistors are arranged at a predetermined interval in a second direction crossing the first direction ([0091]) such that the following expressions (1) and (2) are satisfied:
Xi ≤ Xi + 1 (1)
X1 < Xn (2)
where Xi represents a center position coordinate of an i-th gate electrode of the gate electrodes in the first direction, Xi + 1 represents a center position coordinate of an i+1th gate electrode of the gate electrodes in the first direction, and n represents number of the gate electrodes (Fig. 15A, note that the gate lengths of the unit become successively longer moving from right to left such that there is a diagonal shift in the center position of the gate electrodes moving from right to left).
Considering claim 3, Abe discloses wherein the plurality of the gate electrodes is arranged such that Xi + 1 - Xi takes a positive or negative value that is constant
regardless of locations (annotated Fig. 15A, note that the gate intervals are disclosed to be constant and as can be seen in the annotated Fig. 15A above the center positions of the gate electrodes (arrow in annotated Fig. 15A) have a constant rate of change moving from right to left and left to right) .
Continuing to claim 8, Abe discloses comprising: a gate coupling part (32) electrically coupled to the plurality of the gate electrodes ([0091]); a source coupling part (61) electrically coupled to a plurality of the source electrodes ([0091]); a drain coupling part (71) electrically coupled to a plurality of the drain electrodes ([0091]); a first via (62) in contact with the gate coupling part; and a second via in contact (72) with the drain coupling part, wherein the first via and the second via are disposed opposite to each other with the plurality of the gate electrodes interposed therebetween (Fig. 15A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20090134430 (Abe et al).
Referring to claim 2, Abe discloses forming the gate electrodes.
Abe does not disclose in the configuration shown in Fig. 15A wherein the plurality of the gate electrodes has a length equal to each other. However, Abe discloses several configurations of their invention (Fig. 13A) in which the gate electrodes are formed to have the same length. Abe discloses that with such a configuration it is possible to solve the problem of causing abnormal transistor characteristics, and thus, to provide an excellent semiconductor device having proper characteristics ([0081]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate electrode lengths in order to solve the problem of causing abnormal transistor characteristics, and thus, to provide an excellent semiconductor device having proper characteristics.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20090134430 (Abe et al) as applied to claim 1 above, and further in view of US 20100244050 (Kuraguchi).
Regarding claim 4, Abe discloses forming the plurality of the gate electrodes.
Abe does not disclose wherein the plurality of the gate electrodes is arranged such that Xi + 1 - Xi takes a largest value when i is n/2 or nearly n/2. However, Kuraguchi discloses a gate electrode (transistor configuration ) in which are repeatedly arranged with a cycle "c1" in the cross direction and a cycle "c2" in the longitudinal direction. As shown in FIG. 14, a distance between a gravity center "gt" of the transistor units 12 and a gravity center "gd" of the diode units 14 is expressed as a distance "d1" in the cross direction and a distance "d2" in the longitudinal direction. A half of the cycle "c1/2", a half of the cycle "c 2/2", the distance "d1" and the distance "d2" are equal to or less than twice of the thermal diffusion length. Kuraguchi additionally discloses that the semiconductor device inhibits increasing the element temperatures by arranging the active elements dispersively and defines an interval between the element units formed by the active elements. The element units may be arranged diagonally, in a grid, or in a hexagonal grid. the element units may not be arranged periodically but the distance between the gravity centers of the element units is equal to or less than twice of the thermal diffusion length in order to inhibit increasing the element temperatures ([0088]-[0092]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kuraguchi in the placement of the gate electrodes in order to inhibit increasing the element temperatures.
Pertaining to claim 5, Abe in view of Kuraguchi discloses wherein the plurality of the gate electrodes is arranged such that Xi + 1 - Xi gradually increases as i changes from 1 to n/2 and that Xi + 1 - Xi gradually increases as i changes from n to n/2 (Kuraguchi [0088]-[0089]).
As to claim 6, Abe in view of Kuraguchi discloses wherein Xn - X1 is a length equal to or greater than a length of the gate electrode in the first direction (Abe [0093]).
Concerning claim 7, Abe in view of Kuraguchi discloses wherein a curved line obtained by connecting center positions of the gate electrodes (Abe [0088]-[0089], note that applicant has disclosed that when the multiple gate electrode in the semiconductor device are preferably arranged such that Xi + 1 - Xi gradually increases as i changes from n toward n/2. the center positions are arranged into an S-shape ([0032]) has a length three times or greater than the gate electrode in the first direction (Abe Fig. 15A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20180076295 discloses gate electrode arrangements in order to combat heat dissipation issues (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 04/04/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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