DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 26 and 29 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Takeshi YUASA et. al. (US 20200022249 A1) hereinafter, YUASA.
Regarding claim 26
YUASA discloses
A printed circuit board comprising a signal line located adjacent to a plurality of pads
(YUASA, p. 2, [0031] “On a front surface of the printed circuit board 100 , the ground pads 14, the signal pad 21, the signal line conductor 22, the signal line conductor 23, and the signal line conductor 24 are provided.”)
the plurality of pads arranged in a line from a first pad to a second pad
(YUASA, p. 2, [0027] “… FIG. 1B is a cross-sectional view on arrow of the module 1 taken on the plane of the A-A′ line of FIG. 1A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24 into two parts in a thickness direction.”)
the signal line substantially filling an area bounded by
a first centerline extending through the plurality of pads
(YUASA, p. 4, [0073] “… FIG. 4B is a cross-sectional view on arrow of the module 1B taken on the plane of the A-A′ line of FIG. 4A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24B into two parts in a thickness direction.”)
The signal line 22 substantially filling an area bounded by a first centerline extending through the plurality of pads.
a second centerline of the first pad, a second centerline of the second pad
(YUASA, p. 5, [0077] “On a front surface of the printed circuit board 100B, the ground pads 14, the signal pad 21, the signal line conductor 22, the signal line conductor 23, and the signal line conductor 24B are provided.”)
The signal line 22 substantially filling an area bounded by a second centerline of the first pad 21, a second centerline of the second pad 14.
and a first edge of the signal line that is a distal edge of the signal line relative to the first centerline
(YUASA, p. 5, [0078] “The signal line conductor 24B is a second signal line conductor that extends from the signal line conductor 22 along the periphery of the signal pad 21, and further extends along the periphery of a ground pad 14, as shown in FIG. 4B.”)
The signal line 22 substantially filling an area bounded by a first edge of the signal line 22 that is a distal edge of the signal line 22 relative to the first centerline.
wherein the second centerline of the first pad and the second centerline of the second pad are orthogonal to the first centerline
(YUASA, p. 5, [0080] “Further, because the signal line conductor 24B extends along the periphery of the signal pad 21 and, after that, further extends along the periphery of the ground pad 14, the wire length of the signal line conductor 24B is longer than that of the signal line conductor 24 shown in Embodiment 1.”)
The second centerline of the first pad 21 and the second centerline of the second pad 14 are orthogonal to the first centerline.
the signal line substantially filling the area to an extent that it is spaced from the plurality of pads
(YUASA, p. 5, [0079] “In the board connection structure according to Embodiment 3, a capacitive component is formed between the signal pad 21 and the signal line conductor 24B, like in the case of Embodiment 1, and a capacitive component is further formed between the ground pad 14 and the signal line conductor 24B. This portion between the ground pad 14 and the signal line conductor 24B is referred to as a signal-to-ground capacitance forming portion 28.”)
a shape of a portion of an edge of the signal line in a vicinity of an individual pad substantially identical to a shape of a portion of the edge of the individual pad in a vicinity of the signal line
(YUASA, p. 5, [0081] “In the board connection structure according to Embodiment 3, capacitance needed for matching of impedance is ensured by the capacitive component formed in the inter-signal capacitance forming portion 25, the capacitive component formed in the signal-to-ground capacitance forming portion 28, and the ground capacitance component in the signal line conductor 24B.”)
The shape of the portion of the edge of the signal line 22 in the vicinity of pad 21 is identical to the shape of the portion of the edge of the pad 21 in the vicinity of signal line 22.
Regarding claim 29
YUASA teaches all features of claim 26 as disclosed above and further discloses
The printed circuit board of claim 26, wherein one or more integrated circuit components are attached or connected to the printed circuit board.
(YUASA, p. 1, [0027] “FIG. 1A is a cross-sectional view showing the configuration of a module 1 provided with an inter-board connection structure according to Embodiment 1 of the present disclosure, and shows a view of the module 1 taken along the C-C′ line of FIG. 1B. FIG. 1B is a cross-sectional view on arrow of the module 1 taken on the plane of the A-A′ line of FIG. 1A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24 into two parts in a thickness direction.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over YUASA (US 20200022249 A1) in view of Bilal Ahmad (20090188711), hereinafter Ahmad.
Regarding claim 27
YUASA teaches all features of claim 26 as disclosed above.
YUASA does not explicitly teach
The printed circuit board of claim 26, wherein the plurality of pads are located within a pin field
However, Ahmad discloses
The printed circuit board of claim 26, wherein the plurality of pads are located within a pin field
(Ahmad, p. 1, [0005] “… Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
(Ahmad, p. 1, [0006] “The impedance of a typical signal via of a component pinfield in a typical multilayered PCB 10 with FR4 dielectric is always less than 50 ohms. The impedance depends largely on the diameter of the signal via drill hole 24, the diameter of the anti-pads 34, the dielectric constant of the insulating material, diameter and locations of the signal via pads 28, and spacing of the signal via drill holes 24 and ground via drill holes 18.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA and of Ahmad to yield predictable result of making connection easy in multilayer printed circuit board, thereby reducing design time and costs.
Regarding claim 28
YUASA teaches all features of claim 26 as disclosed above.
YUASA does not explicitly teach
The printed circuit board of claim 26, the signal line substantially filling the area to a further extent that it is spaced from one or more additional signal lines.
However, Ahmad teaches
The printed circuit board of claim 26, the signal line substantially filling the area to a further extent that it is spaced from one or more additional signal lines.
(Ahmad, p. 1, [0005] “The traces 32 are arranged as signal straddling differential pairs, for instance depicted as a first differential pair 36a composed of a lower trace 38a and an upper trace 40a and an adjacent second differential pair 36b composed of a lower trace 38b and upper trace 40b. Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
The figure clearly shows the signal lines substantially filling the area.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA and of Ahmad to yield predictable result of making connection easy in multilayer printed circuit board, thereby reducing design time and costs as well as having signal lines spaced apart minimizing cross talk etc.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over YUASA (US 20200022249 A1) in view of Ravi Kesarwani et. al. (US 20060101368 A1) hereinafter Kesarwani
YUASA teaches all features of claim 26 as disclosed above.
YUASA does not explicitly teach
The printed circuit board of claim 29, wherein the one or more integrated circuit components a processing unit and/or a memory.
However Kesarwani discloses
The printed circuit board of claim 29, wherein the one or more integrated circuit components a processing unit and/or a memory.
(Kesarwani, p. 15, p. 7, [0079] “… In some cases, a library may be a database identifying actual physical components that can be used on a PCB (e.g., resistors, capacitors, memory chips, etc.);”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA and of Kesarwani to make sure that the printed circuit board has useful components.
Claims 31, 38, and 41-45 are rejected under 35 U.S.C. 103 as being unpatentable over YUASA (US 20200022249 A1) in view of Ravi Kesarwani et. al. (US 20060101368 A1) hereinafter Kesarwani and Bilal Ahmad (20090188711), hereinafter Ahmad.
Regarding claim 31
YUASA discloses section b-c of claim 31
b. modifying a portion of a signal line of the printed circuit board layout located adjacent to a plurality of pads of the printed circuit board layout arranged in a line from a first pad to a second pad
(YUASA, p. 1, [0009] “… a first signal line conductor provided in the outer layer or the inner layer of the first dielectric board; a second signal line conductor extending in a direction from the first signal line conductor to the first signal pad, and forming a capacitive component between the second signal line conductor and the first signal pad; a third signal line conductor branching and extending from a connecting portion between the first signal line conductor and the second signal line conductor, and electrically connected to the first signal pad; a second signal pad provided in an outer layer of a second dielectric board; a second ground pad provided in the outer layer of the second dielectric board and in an area surrounding the second signal pad; a signal bump electrically connecting the first signal pad and the second signal pad; and a ground bump electrically connecting the first ground pad and the second ground pad.”)
(YUASA, p. 2, [0027] “… FIG. 1B is a cross-sectional view on arrow of the module 1 taken on the plane of the A-A′ line of FIG. 1A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24 into two parts in a thickness direction.”)
a centerline extending through the plurality of pads
(YUASA, p. 4, [0073] “… FIG. 4B is a cross-sectional view on arrow of the module 1B taken on the plane of the A-A′ line of FIG. 4A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24B into two parts in a thickness direction.”)
The signal line 22 substantially filling an area bounded by a first centerline extending through the plurality of pads.
YUASA does not explicitly teach sections a, d, and e of claim 31
accessing a printed circuit board layout from a layout database
modifying the portion of the signal line comprising extending an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
and storing the printed circuit board layout comprising the modified signal line in the layout database.
However Kesarwani (US 20060101368 A1) teaches sections a and e of claim 31.
accessing a printed circuit board layout from a layout database
(Kesarwani, p. 2, [0012] ”In at least some embodiments of the invention, logical design data for a PCB is stored in a database. The design data is organized according to a connectivity-based data model. Also stored are profiles for multiple users. The profile data for each user specifies logical design data elements accessible by that user and PCB design software to be provided to that user for accessing or editing logical design data. In accordance with the stored profiles, elements of the logical design data and one or more PCB design software programs are transmitted to client computers. The PCB design software may include plug-ins executable within a web browser at a client. Logical design data edits are received from the clients and applied to the logical design data stored in the database.”)
(Kesarwani, p. 3, [0027] “FIGS. 8A-8J show access and editing of design data according to at least some embodiments of the invention.”)
(Kesarwani, p. 9, [0094] “FIG. 7 is a block diagram showing an architecture for an EDA system according to at least some embodiments of the invention. Design database 50 is located at the bottom of FIG. 7. Design database 50 stores data objects for one or more designs. … Data in database 50 is accessed through a collection of data APIs 56.”)
(Kesarwani, p. 15, [0134] “The LLOM generally includes one or more Board objects (block 120). Each board corresponds to layout data for a particular PCB.”)
and storing the printed circuit board layout comprising the modified signal line in the layout database.
(Kesarwani, p. 2, [0013] “Additional embodiments of the invention include storing PCB logical design data which is organized according to a connectivity-based data model.”)
(Kesarwani, p. 15, [0134] “The LLOM generally includes one or more Board objects (block 120). Each board corresponds to layout data for a particular PCB.”)
(Kesarwani, p. 26, claim 44 “A method for editing a printed circuit board (PCB) design, comprising: storing logical design data for a PCB in a database; storing layout data for the PCB in the database, wherein elements of the layout data are mapped to elements of the logical design data; and automatically modifying layout data elements in response to edits to logical design data elements.”)
(Kesarwani, p. 3, [0053] “… Included in FIG. 1 are two flip-flops 2 and 4, an AND gate 6 and a four-way AND gate 8. Also shown in FIG. 1 are interconnections between inputs and outputs of these circuit elements, as well as connections to various signal lines (e.g., "Clock," "Data1," etc.) connected to other circuit elements not shown in FIG. 1.”)
(Kesarwani, p. 3, [0053] “… Included in FIG. 1 are two flip-flops 2 and 4, an AND gate 6 and a four-way AND gate 8. Also shown in FIG. 1 are interconnections between inputs and outputs of these circuit elements, as well as connections to various signal lines (e.g., "Clock," "Data1," etc.) connected to other circuit elements not shown in FIG. 1.”)
YUASA and Kesarwani do not explicitly teach section d of claim 31.
modifying the portion of the signal line comprising extending an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
However, Ahmad discloses
modifying the portion of the signal line comprising extending an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
(Ahmad, p. 1, [0005] “… Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
Extended signal lines consistent with the above claim and the keep-out region is very much visible in Fig. 1.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 38
YUASA teaches section c-d of claim 38.
modify a portion of a signal line of the printed circuit board layout located adjacent to a plurality of pads of the printed circuit board layout arranged in a line from a first pad to a second pad
(YUASA, p. 1, [0009] “… a first signal line conductor provided in the outer layer or the inner layer of the first dielectric board; a second signal line conductor extending in a direction from the first signal line conductor to the first signal pad, and forming a capacitive component between the second signal line conductor and the first signal pad; a third signal line conductor branching and extending from a connecting portion between the first signal line conductor and the second signal line conductor, and electrically connected to the first signal pad; a second signal pad provided in an outer layer of a second dielectric board; a second ground pad provided in the outer layer of the second dielectric board and in an area surrounding the second signal pad; a signal bump electrically connecting the first signal pad and the second signal pad; and a ground bump electrically connecting the first ground pad and the second ground pad.”)
(YUASA, p. 2, [0027] “… FIG. 1B is a cross-sectional view on arrow of the module 1 taken on the plane of the A-A′ line of FIG. 1A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24 into two parts in a thickness direction.”)
a centerline extending through the plurality of pads
(YUASA, p. 4, [0073] “… FIG. 4B is a cross-sectional view on arrow of the module 1B taken on the plane of the A-A′ line of FIG. 4A. The A-A′ line divides each of the following components: ground pads 14, a signal pad 21, a signal line conductor 22, a signal line conductor 23, and a signal line conductor 24B into two parts in a thickness direction.”)
The signal line 22 substantially filling an area bounded by a first centerline extending through the plurality of pads.
YUASA does not teach sections a-b and e-f of claim 38
One or more computer-readable storage media storing computer- executable instructions that, that, when executed, cause a computing system to
access a printed circuit board layout from a layout database
to modify the portion of the signal line comprising to extend an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
and store the printed circuit board layout comprising the modified signal line in the layout database.
However, Kesarwani discloses section a-b and f of claim 38.
One or more computer-readable storage media storing computer- executable instructions that, that, when executed, cause a computing system to
(Kesarwani, p. 9, [0094] “FIG. 7 is a block diagram showing an architecture for an EDA system according to at least some embodiments of the invention. … Similarly, various aspects of the invention can be embodied as programming instructions on a medium readable by a computer or other device.”)
access a printed circuit board layout from a layout database
(Kesarwani, p. 2, [0012] ”In at least some embodiments of the invention, logical design data for a PCB is stored in a database. The design data is organized according to a connectivity-based data model. Also stored are profiles for multiple users. The profile data for each user specifies logical design data elements accessible by that user and PCB design software to be provided to that user for accessing or editing logical design data. In accordance with the stored profiles, elements of the logical design data and one or more PCB design software programs are transmitted to client computers. The PCB design software may include plug-ins executable within a web browser at a client. Logical design data edits are received from the clients and applied to the logical design data stored in the database.”)
(Kesarwani, p. 3, [0027] “FIGS. 8A-8J show access and editing of design data according to at least some embodiments of the invention.”)
(Kesarwani, p. 9, [0094] “FIG. 7 is a block diagram showing an architecture for an EDA system according to at least some embodiments of the invention. Design database 50 is located at the bottom of FIG. 7. Design database 50 stores data objects for one or more designs. … Data in database 50 is accessed through a collection of data APIs 56.”)
(Kesarwani, p. 15, [0134] “The LLOM generally includes one or more Board objects (block 120). Each board corresponds to layout data for a particular PCB.”)
and store the printed circuit board layout comprising the modified signal line in the layout database.
(Kesarwani, p. 2, [0013] “Additional embodiments of the invention include storing PCB logical design data which is organized according to a connectivity-based data model.”)
(Kesarwani, p. 15, [0134] “The LLOM generally includes one or more Board objects (block 120). Each board corresponds to layout data for a particular PCB.”)
(Kesarwani, p. 26, claim 44 “A method for editing a printed circuit board (PCB) design, comprising: storing logical design data for a PCB in a database; storing layout data for the PCB in the database, wherein elements of the layout data are mapped to elements of the logical design data; and automatically modifying layout data elements in response to edits to logical design data elements.”)
YUASA and Kesarwani do not explicitly teach sections e of claim 38.
to modify the portion of the signal line comprising to extend an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
However Ahmad teaches section e of claim 38.
to modify the portion of the signal line comprising to extend an edge of the signal line that is proximate to the centerline to an edge of a first keep-out region associated with the centerline and to edges of a plurality of second keep-out regions associated with the plurality of pads
(Ahmad, p. 1, [0005] “… Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
Extended signal lines consistent with the above claim and the keep-out region is very much visible in Fig. 1.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 41
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA and Kesarwani do not teach
The one or more computer-readable storage media of claim 38, wherein individual of the plurality of second keep-out regions extend from a via associated with individual of the plurality of pads and an extent of the individual of the plurality of second keep- out regions is based on a via-to-metal design rule spacing.
However Ahmad further discloses
The one or more computer-readable storage media of claim 38, wherein individual of the plurality of second keep-out regions extend from a via associated with individual of the plurality of pads and an extent of the individual of the plurality of second keep- out regions is based on a via-to-metal design rule spacing.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
The figures clearly show plurality of keep-out regions, each one extending from via (example 20 and 30) associated with individual of the plurality of pads (example 14 and 28), and as mentioned above with optimized spacing (which would have considered via-to-metal design rule spacing).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 42
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA and Kesarwani do not teach
The one or more computer-readable storage media of claim 38, wherein individual of the plurality of second keep-out regions extend from one of the plurality of pads and an extent of the individual of plurality of second keep-out regions is a metal-to-metal design rule spacing.
However Ahmad further discloses
The one or more computer-readable storage media of claim 38, wherein individual of the plurality of second keep-out regions extend from one of the plurality of pads and an extent of the individual of plurality of second keep-out regions is a metal-to-metal design rule spacing.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
The figures clearly show plurality of keep-out regions, each one extending from individual of the plurality of pads (example 14 and 28), and as mentioned above with optimized spacing (which would have considered metal-to-metal design rule spacing).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 43
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA does not teach
The one or more computer-readable storage media of claim 38, wherein the modified signal line is represented in the printed circuit board layout stored in the layout database as a single shape.
However Kesarwani further discloses
The one or more computer-readable storage media of claim 38, wherein the modified signal line is represented in the printed circuit board layout stored in the layout database as a single shape.
(Kesarwani, p. 2, [0013] “Additional embodiments of the invention include storing PCB logical design data which is organized according to a connectivity-based data model.”)
(Kesarwani, p. 15, [0134] “The LLOM generally includes one or more Board objects (block 120). Each board corresponds to layout data for a particular PCB.”)
(Kesarwani, p. 26, claim 44 “A method for editing a printed circuit board (PCB) design, comprising: storing logical design data for a PCB in a database; storing layout data for the PCB in the database, wherein elements of the layout data are mapped to elements of the logical design data; and automatically modifying layout data elements in response to edits to logical design data elements.”)
(Kesarwani, p. 14, [0126] “Although layout design may be based upon information generated during the logical design process, there is often not a one-to-one correspondence between data types in the front and back ends. As seen in FIG. 2, for example, the signal path from port A_3 to port C_1 includes three nets: E_c, Net11 and F_a. In the layout domain, however, this is a single net. As another example, cells E and F will generally have little meaning or use in the layout domain. In other words, a hierarchical logical design must be "flattened" into a collection of parts at the same level. As yet another example, and as previously described, multiple logical elements could be implemented as different slots of the same physical element.”)
“the signal path from port A_3 to port C_1 includes three nets: E_c, Net11 and F_a. In the layout domain, however, this is a single net” infers that the modified signal line is saved as a single shape.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 44
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA and Kesarwani do not teach
The one or more computer-readable storage media of claim 38, wherein the centerline extending through the plurality of pads is a first centerline, the portion of the signal line is located between a second centerline associated with the first pad and a second centerline associated with the second pad, the second centerline associated with the first pad and the second centerline associated with the second pad being orthogonal to the first centerline.
However Ahmad further discloses
The one or more computer-readable storage media of claim 38, wherein the centerline extending through the plurality of pads is a first centerline, the portion of the signal line is located between a second centerline associated with the first pad and a second centerline associated with the second pad, the second centerline associated with the first pad and the second centerline associated with the second pad being orthogonal to the first centerline.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
(Ahmad, p. 1, [0005] “The traces 32 are arranged as signal straddling differential pairs, for instance depicted as a first differential pair 36a composed of a lower trace 38a and an upper trace 40a and an adjacent second differential pair 36b composed of a lower trace 38b and upper trace 40b. Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
The figures clearly show that the “second” centerlines associated with signal lines 38a and 40a and 38b and 40b are orthogonal to the “first” centerline going through the plurality of pads 20.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 45
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA and Kesarwani do not teach
The one or more computer-readable storage media of claim 38, wherein to extend the edge of the signal line that is proximate to the centerline to the edge of the first keep- out region associated with the centerline and to the edges of the plurality of second keep-out regions associated with the plurality of pads comprises:
extending the edge of the signal line that is proximate to the centerline to the centerline
extending the edge of the signal line that is proximate to the centerline to pad edges of the plurality of pads
and pulling the edge of the signal line that is proximate to the centerline back to the edge of the first keep-out region and to the edges of the plurality of second keep-out regions.
However Ahmad further discloses
The one or more computer-readable storage media of claim 38, wherein to extend the edge of the signal line that is proximate to the centerline to the edge of the first keep- out region associated with the centerline and to the edges of the plurality of second keep-out regions associated with the plurality of pads comprises:
extending the edge of the signal line that is proximate to the centerline to the centerline
extending the edge of the signal line that is proximate to the centerline to pad edges of the plurality of pads
and pulling the edge of the signal line that is proximate to the centerline back to the edge of the first keep-out region and to the edges of the plurality of second keep-out regions.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
(Ahmad, p. 1, [0005] “The traces 32 are arranged as signal straddling differential pairs, for instance depicted as a first differential pair 36a composed of a lower trace 38a and an upper trace 40a and an adjacent second differential pair 36b composed of a lower trace 38b and upper trace 40b. Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
The Fig.1 and Fig. 2 make abundantly clear that signal line 32 extending the edge of the signal line that is proximate to the centerline to the centerline, 40b extending the edge of the signal line that is proximate to the centerline to pad edges of the plurality of pads, and both pulling the edge of the signal line that is proximate to the centerline back to the edge of the first keep-out region and to the edges of the plurality of second keep-out regions.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani and of Ahmad to yield predictable result of a printed circuit board designed and validated against all design rule check.
Claims 32-35 and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over YUASA, Kesarwani and of Ahmad as applied to claim 31 above, and further in view of Edward Hugh Welbon et. al. (US 20040199844 A1) hereinafter Welbon.
Regarding claim 32
YUASA, Kesarwani and of Ahmad teach all features of claim 31 as disclosed above.
YUASA, Kesarwani and of Ahmad do not explicitly teach
The method of claim 31, wherein an extent of the first keep-out region is based on a metal-to-metal design rule spacing.
However, Welbon teaches
The method of claim 31, wherein an extent of the first keep-out region is based on a metal-to-metal design rule spacing.
(Welbon, p. 1, [0004] “Circuit boards come in many different types. One common type of circuit board is a printed circuit board. Printed circuit boards generally have one or more layers of insulating or dielectric material which may be laminated together. Each layer may include multiple signal paths or "signal traces" which are used to propagate signals.”)
(Welbon, p. 1, [0008] “Generally, design rules allow the traces to be routed with as much space between traces as possible. However, depending on such factors as the density of the signal traces and circuit components, signal traces and even vias may necessarily be routed relatively close together.”)
(Welbon, p. 1, [0037] “As described above, in the illustrated embodiment, ground plane 485 includes a copper sheet 550, although it is noted that other embodiments may use other conductive materials for the conductive surface. Ground plane 485 may serve as a circuit ground. … Ground plane 485 also includes a keep out region 540. Keep out region 540 may provide a region where no copper sheet exists. Thus, contact pad 495 and driven test via 565 do not contact copper sheet 550.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani, Ahmad, and of Welbon to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 33
YUASA, Kesarwani, Ahmad, and Welbon teach all features of claim 32.
YUASA, Kesarwani, and Ahmed further discloses
The method of claim 32, wherein individual of the plurality of second keep-out regions extend from a via associated with individual of the plurality of pads and an extent of the individual of the plurality of second keep-out regions is based on a via-to-metal design rule spacing.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
The figures clearly show plurality of keep-out regions, each one extending from via (example 20 and 30) associated with individual of the plurality of pads (example 14 and 28), and as mentioned above with optimized spacing (which would have considered via-to-metal design rule spacing).
Regarding claim 34
YUASA, Kesarwani, Ahmad, and Welbon teach all features of claim 32.
YUASA, Kesarwani, and Ahmed further discloses
The method of claim 32, wherein individual of the plurality of second keep-out regions extend from one of the plurality of pads and an extent of the individual of the plurality of second keep-out regions is a metal-to-metal design rule spacing.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
The figures clearly show plurality of keep-out regions, each one extending from individual of the plurality of pads (example 14 and 28), and as mentioned above with optimized spacing (which would have considered metal-to-metal design rule spacing).
Regarding claim 35
YUASA, Kesarwani, Ahmad, and Welbon teach all features of claim 32.
YUASA, Kesarwani, and Ahmed further discloses
The method of claim 32, wherein the centerline extending through the plurality of pads is a first centerline, the portion of the signal line is located between a second centerline associated with the first pad and a second centerline associated with the second pad, the second centerline associated with the first pad and the second centerline associated with the second pad being orthogonal to the first centerline.
(Ahmad, p. 1, [0007] “FIG. 1 illustrates a conventional printed circuit board (PCB) having signal straddling differential pairs of traces in a connector pinfield.”)
(Ahmad, p. 1, [0008] “FIG. 2 illustrates a PCB having ground straddling differential pairs of traces in a connector pinfield with optimized spacing for consistent impedance and skew compensation.”)
(Ahmad, p. 1, [0005] “The traces 32 are arranged as signal straddling differential pairs, for instance depicted as a first differential pair 36a composed of a lower trace 38a and an upper trace 40a and an adjacent second differential pair 36b composed of a lower trace 38b and upper trace 40b. Each pair 36a, 36b approaches a respective horizontal row of signal vias 30 from slightly below and slightly above centerline, respectively, and spreading apart to clear opposite sides of each anti-pad 34 for the respective row of anti-pads 34 until a particular signal via 30 is reached for each trace 38a, 38b, 40a, 40b, or until the differential pair clears through the pinfield.”)
The figures clearly show that the “second” centerlines associated with signal lines 38a and 40a and 38b and 40b are orthogonal to the “first” centerline going through the plurality of pads 20.
Regarding claim 39
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above.
YUASA, Kesarwani and of Ahmad do not explicitly teach
The one or more computer-readable storage media of claim 38, wherein an extent of the first keep-out region is based on a metal-to-metal design rule spacing.
However, Welbon teaches
The one or more computer-readable storage media of claim 38, wherein an extent of the first keep-out region is based on a metal-to-metal design rule spacing.
(Welbon, p. 1, [0004] “Circuit boards come in many different types. One common type of circuit board is a printed circuit board. Printed circuit boards generally have one or more layers of insulating or dielectric material which may be laminated together. Each layer may include multiple signal paths or "signal traces" which are used to propagate signals.”)
(Welbon, p. 1, [0008] “Generally, design rules allow the traces to be routed with as much space between traces as possible. However, depending on such factors as the density of the signal traces and circuit components, signal traces and even vias may necessarily be routed relatively close together.”)
(Welbon, p. 1, [0037] “As described above, in the illustrated embodiment, ground plane 485 includes a copper sheet 550, although it is noted that other embodiments may use other conductive materials for the conductive surface. Ground plane 485 may serve as a circuit ground. … Ground plane 485 also includes a keep out region 540. Keep out region 540 may provide a region where no copper sheet exists. Thus, contact pad 495 and driven test via 565 do not contact copper sheet 550.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani, Ahmad, and of Welbon to yield predictable result of a printed circuit board designed and validated against all design rule check.
Regarding claim 40
YUASA, Kesarwani and of Ahmad teach all features of claim 38 as disclosed above
YUASA, Kesarwani and of Ahmad do not explicitly teach
The one or more computer-readable storage media of claim 39, wherein the metal-to-metal design rule spacing is set by a signal integrity performance requirement.
However, Welbon discloses
The one or more computer-readable storage media of claim 39, wherein the metal-to-metal design rule spacing is set by a signal integrity performance requirement.
(Welbon, p. 1, [0006] “The signal traces are typically thin metallic "wires" which have been etched from a pattern which has been printed onto a metal layer which may be bonded to the surface of the circuit board. The metal is generally copper or some other similar conductive copper alloy. Depending on the type of process used to manufacture the circuit board, the unused metal may be etched away leaving the signal traces and any other metallic contact surfaces intact.”)
(Welbon, p. 1, [0008] “Generally, design rules allow the traces to be routed with as much space between traces as possible. However, depending on such factors as the density of the signal traces and circuit components, signal traces and even vias may necessarily be routed relatively close together.”)
(Welbon, p. 1, [0009] “At high frequencies, the traces on a circuit board may act like transmission lines, thus certain trace characteristics become important when considering signal integrity.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani, Ahmad, and of Welbon to yield predictable result of a printed circuit board designed and validated against all design rule check.
Claim 36-37 is rejected under 35 U.S.C. 103 as being unpatentable over YUASA, Kesarwani, Ahmad, and of Welbon as applied to claim32 above, and further in view of Douglas A. Baska et. al. (US 20120081873 A1) hereinafter Baska.
Regarding claim 36
YUASA, Kesarwani, Ahmad, and Welbon teach all features of claim 32.
YUASA, Kesarwani, Ahmad, and Welbon do not teach
The method of claim 32, further comprising generating a photolithography mask to be used during manufacture of a printed circuit board comprising the modified portion of the signal line.
However, Baska discloses
The method of claim 32, further comprising generating a photolithography mask to be used during manufacture of a printed circuit board comprising the modified portion of the signal line.
(Baska, p. 5, [0040] “The computer system described above and the method described in the flow above may be used in a design, simulation, test, layout, and manufacture of circuit boards on which integrated circuit chips may be connected according to some embodiments. The method may include includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of structures and/or devices described above and shown in FIGS. 1A-1C, 2, 3, 4, 5, 6 and 7. … For example, machines may include machines and/or equipment for generating masks, computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani, Ahmad, Welbon, and of Baska to yield predictable result of generating masks for manufacturing printed circuit board fully designed, tested and validated against all design rule check.
Regarding claim 37
YUASA, Kesarwani, Ahmad, and Welbon teach all features of claim 32.
YUASA, Kesarwani, Ahmad, and Welbon do not teach
The method of claim 32, further comprising manufacturing a printed circuit board comprising the modified portion of the signal line.
However, Baska discloses
The method of claim 32, further comprising manufacturing a printed circuit board comprising the modified portion of the signal line.
(Baska, p. 5, [0040] “The computer system described above and the method described in the flow above may be used in a design, simulation, test, layout, and manufacture of circuit boards on which integrated circuit chips may be connected according to some embodiments. The method may include includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of structures and/or devices described above and shown in FIGS. 1A-1C, 2, 3, 4, 5, 6 and 7. … For example, machines may include machines and/or equipment for generating masks, computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of YUASA, Kesarwani, Ahmad, Welbon, and of Baska to yield predictable result of manufacturing printed circuit board fully designed, tested and validated against all design rule check.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. The examiner can normally be reached Mon-Fri:8:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
Prosecution Insights