DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2010/0090781) in view of CN’351 (CN111200351, cited in IDS).
Regarding claim 1, Yamamoto discloses a device module comprising: a first layer (Fig.1A, numeral 1), a second layer (5), and a first functional layer (lower part of (9)) and a second functional layer (upper part of (9)) between the first (1) and the second layer (5), wherein the first functional layer includes a plurality of capacitors (2), (3) and a plurality of via electrodes (7), (8) isolated from the plurality of capacitors; (2), (3) a plurality of inductors (6) are formed in the second functional layer (upper part of (9)), each of which is arranged along a thickness direction of the second functional layer so that a first terminal (lower part of (6)) of the inductor (6) is electrically coupled with the first layer (1) through corresponding one of the via electrodes (7), (8), and a second terminal of the inductor (upper part of (6)) is electrically coupled with the second layer (5).
Yamamoto does not disclose that the first and the second layers are conductive. Yamamoto however discloses forming external connections terminals ([0093]; Fig. 1B). And CN’351 discloses connection of a fist layer to a wiring (Fig.2, numeral 21) and a second layer to a lead frame (6).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to modify Yamamoto with CN’351 to have conductive the first and the second layer for the purpose of proving external connections to the packaging module.
Regarding claim 2, CN’351 discloses a driver chip above the first conductive layer, wherein the driver chip (Fig.2, numeral 1) is electrically coupled to the plurality of capacitors (Yamamoto, Fig. 1A, numerals 2, 3; CN’351, claim 3) in the first functional layer and the plurality of inductors (CN’351, numeral 4) in the second functional layer through the first conductive layer (21).
Regarding claim 3, CN’351 discloses wherein the driver chip comprises a multi-phase switching power supply chip (claim 2).
Regarding claim 6, Yamamoto discloses an inductor-capacitor array, comprising: a first layer (Fig.1A, numeral 1), a second layer (5), and a lamination structure between the first layer (1) and the second layer (5), the lamination structure comprising an inductor layer (6) and a capacitor layer (2), (30, wherein the capacitor layer includes a plurality of capacitors (2), (3) and a plurality of via electrodes (7), (8) isolated from the plurality of capacitors; a plurality of inductors are formed in the inductor layer, each of which is arranged along a thickness direction of the inductor layer so that a first terminal of the inductor is electrically coupled with the first conductive layer through corresponding one of the via electrodes, and a second terminal of the inductor is electrically coupled with the second conductive layer.
Yamamoto does not disclose that the first and the second layers are conductive. Yamamoto however discloses forming external connections terminals ([0093]; Fig. 1B). And CN’351 discloses connection of a fist layer to a wiring (Fig.2, numeral 21) and a second layer to a lead frame (6).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to modify Yamamoto with CN’351 to have conductive the first and the second layer for the purpose of proving external connections to the packaging module.
Regarding claim 15, Yamamoto discloses forming a lamination structure comprising an inductor layer (6) and a capacitor layer (2); (3) which are laminated (Fig.2G);; and dividing the lamination structure into a plurality of sub-regions through a first scribe lane and a second scribe lane (Figs. 3A-3C), wherein each sub-region comprises a plurality of inductor-capacitor cells ([0116]-[0118]) ; wherein adjacent sub-regions are separated into a plurality of device modules (]0118]).
Yamamoto does not disclose forming a first conductive layer on a first surface of the lamination structure; forming a second conductive layer on a second surface of the lamination structure opposite to the first surface.
Yamamoto however discloses forming external connections terminals ([0093]; Fig. 1B). And CN’351 discloses connection of a fist layer to a wiring (Fig.2, numeral 21) and a second layer to a lead frame (6).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to modify Yamamoto with CN’351 to have form a first conductive layer on a first surface of the lamination structure; forming a second conductive layer on a second surface of the lamination structure opposite to the first surface for the purpose of proving external connections to the packaging module.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of CN’351 as applied to claim 6 above, and further in view of Lu (US 2019/0115149).
Regarding claim 8, Yamamoto does not disclose wherein the inductor layer comprises: a core; and a plurality of coils in the core, each of which is formed by winding around an axis along a thickness direction of the core, and both ends of which are led out from opposite end surfaces of the core in the thickness direction.
Lu however discloses wherein the inductor layer comprises: a core; and a plurality of coils in the core, each of which is formed by winding around an axis along a thickness direction of the core, and both ends of which are led out from opposite end surfaces of the core in the thickness direction ([0036]; Fig. 2A).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Yamamoto with Lu to have the inductor layer comprising: a core; and a plurality of coils in the core, each of which is formed by winding around an axis along a thickness direction of the core, and both ends of which are led out from opposite end surfaces of the core in the thickness direction for the purpose of enhancing the mechanical stability of the magnetic assembly (Lu, [0055]).
Regarding claim 9, Lu discloses wherein the core is formed by sealing the plurality of coils with a sealing material by a resin molding method or an integral die-casting method (Fig.2; note: “the core is formed…” is a product-by-process limitation. And according to MPEP 2113, [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)).
Regarding claim 10, Yamamoto discloses plurality of first scribe lanes (Fig.3A, numerals 15) extending in a first direction and a plurality of second scribe lanes (15) extending in a second direction, the first and second scribe lanes crossing each other to divide the lamination structure into a plurality of sub-regions, each sub-region comprising a plurality of inductor-capacitor cells (Figs. 3A-3C; [0116]-[0118]) .
Allowable Subject Matter
Claims 4, 5, 7, 11-14, 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest that each of the plurality of via electrodes penetrates through the upper electrode plate, the capacitor dielectric layer, and the lower electrode plate as required by claims 4 and 7.
The search of the prior art does not disclose or reasonably suggest a plurality of pins above the first conductive layer, wherein the plurality of pins are respectively disposed at two sides of the driver chip; and an encapsulation layer which covers the driver chip and exposed portions of the first conductive layer as required by claim 5.
The search of the prior art does not disclose or reasonably suggest a plurality of driver chips respectively in the plurality of sub-regions, in each sub-region, the plurality of inductor-capacitor cells being electrically coupled to corresponding one of the pluralities of driver chips through the first conductive layer as required by claim 11.
The search of the prior art does not disclose or reasonably suggest wherein the plurality of through holes penetrate through the upper electrode plate, the capacitor dielectric layer and the lower electrode plate as required by claim 16.
Conclusion
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891