DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by U.S. Patent Application Publication Number 2019/0081060 A1 to Lu et al., “Lu”.
Regarding claim 1, Lu discloses a three-dimensional flash memory (e.g. FIG. 20,21A,22B) with an improved stack connection, the three-dimensional flash memory comprising:
a plurality of stack structures (formed from FIG. 11A and 11B lower stack 2 and formed from FIG. 12 upper stack 15, ¶ [0047],[0081]), wherein each of the plurality of stack structures includes:
a plurality of word lines (FIG. 22A,22B conductors 40, ¶ [0112]) extending in a horizontal direction and stacked alternately with each other in a vertical direction; and
at least one cell string extending through the plurality of word lines in the vertical direction, wherein the at least one cell string includes a channel layer (from FIG. 5 channel 11, ¶ [0067] and FIG. 16 channel 23, ¶ [0095]) extending in the vertical direction and a charge storage layer (8, ¶ [0061]) formed to surround the channel layer; and
at least one buffer layer (14, ¶ [0079]-[0080]) disposed between adjacent ones of the plurality of stack structures arranged in the vertical direction, wherein the least one buffer layer (14) connects the respective channel layers of the adjacent ones of the plurality of stack structures to each other (as pictured).
Regarding claim 2, Lu discloses the three-dimensional flash memory of claim 1, and Lu further anticipates wherein the at least one buffer layer (14) has a size and a position set such that the at least one buffer layer accommodates (i.e. connects) both the respective channel layers of the adjacent ones of the plurality of stack structures in a plan view of the three-dimensional flash memory (as evidenced by the side-profile, similar to Applicant’s FIG. 7F buffer 714 connects channels in side-view and therefore necessarily also in plan view).
Examiner’s Note: the language of claim 2 of “accommodates” is determined to be satisfied if the buffer connects the lower and upper channels and is deemed definite as much as the subject matter permits, see e.g. MPEP 2173.05 which states in part:
a claim limitation specifying that a certain part of a pediatric wheelchair be "so dimensioned as to be insertable through the space between the doorframe of an automobile and one of the seats" was held to be definite. Orthokinetics, Inc. v. Safety Travel Chairs, Inc., 806 F.2d 1565, 1 USPQ2d 1081 (Fed. Cir. 1986). The court stated that the phrase "so dimensioned" is as accurate as the subject matter permits, noting that the patent law does not require that all possible lengths corresponding to the spaces in hundreds of different automobiles be listed in the patent, let alone that they be listed in the claims.
Regarding claim 3, Lu discloses the three-dimensional flash memory of claim 1, and Lu further anticipates wherein the at least one buffer layer (14) is made of the same material (silicon, ¶ [0079]) as a material constituting the respective channel layers of the adjacent ones of the plurality of stack structures (11 is silicon ¶ [0067], 23 is silicon ¶ [0095]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2019/0081060 A1 to Lu et al., “Lu”, in view of U.S. Patent Application Publication Number 2023/0033086 A1 to Wang et al., “Wang”.
Regarding claim 4, Lu discloses a method for manufacturing a three-dimensional flash memory (e.g. FIG. 20,21A,22B) with an improved stack connection, the method comprising:
preparing (FIG. 1) a lower stack structure (2) including:
a plurality of word lines (when replace with 40, ¶ [0112]) extending in a horizontal direction and stacked alternately with each other in a vertical direction; and
at least one hole (FIG. 5 hole 5) extending through the plurality of word lines in the vertical direction;
forming (FIG. 3) a charge storage layer (8, ¶ [0061]) having an inner hole defined therein in the at least one hole of the lower stack structure;
disposing (FIG. 11A,11B) at least one buffer layer (14, ¶ [??]) on a top surface (one of the pluralit of top surfaces) of the lower stack structure;
forming (FIG. 12) an upper stack structure on top of the lower stack structure on which the at least one buffer layer has been disposed, wherein the upper stack structure including:
a plurality of word lines (when replace with 40, ¶ [0112]) extending in the horizontal direction and stacked alternately with each other in the vertical direction; and
at least one hole (FIG. 13 hole 18) extending through the plurality of word lines in the vertical direction;
forming (FIG. 15) a charge storage layer (20, ¶ [0090]) having an inner hole defined therein in the at least one hole of the upper stack structure;
removing (FIG. 15) a portion of the at least one buffer layer (14) corresponding to the inner hole of each of the lower stack structure and the upper stack structure, wherein the inner hole of the lower stack structure and the inner hole of the upper stack structure communicate with each other (electrically connected) by removing the portion of the at least one buffer layer; and
forming (FIG. 16) a channel layer (23, ¶ [0095]) in an integrated manner (i.e. electrically connected) in the respective inner holes of the lower stack structure and the upper stack structure.
Although Lu teaches forming word lines (conductors 40) in the stack, Lu fails to clearly teach wherein the replacement process for forming the word lines occurs prior to forming the one hole such that the hole extends through the plurality of word lines in the vertical direction.
Wang teaches forming (FIG. 3A) a stack (memory deck 102a, ¶ [0029],[0030]) including a plurality of word lines (106, ¶ [0031]) prior to forming a trench (FIG. 3B trench 302a, ¶ [0051]), and similarly forming (FIG. 3H) a plurality of word lines (106) prior to forming the trench (302b, ¶ [0061]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Lu by forming the stack including the word lines already formed as taught by Wang in order to either 1) eliminate the step of needing to remove the sacrificial layer and replace with word line material layer, and/or 2) in order to form varying width channels without compromising or sacrificing the erase performance and/or cell electrostatics performance of the memory array (Wang ¶ [0017],[0018]) and/or 3) since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art could have and would have found it obvious to apply (B) Simple substitution of forming the word lines prior to forming the memory trenches rather than after forming the trenches with the predictable and desired result of forming suitable stacked three-dimensional flash memory structures.
Regarding claim 5, Lu in view of Wang yields the method of claim 4, and Lu further teaches wherein the disposing of the at least one buffer layer (14) includes forming the at least one buffer layer so as to have a size and a position set such that the at least one buffer layer accommodates (i.e. connects) both the respective inner holes of the lower stack structure and the upper stack structure in a plan view of the three-dimensional flash memory (as evidenced by the side-profile, similar to Applicant’s FIG. 7F buffer 714 connects channels in side-view and therefore necessarily also in plan view).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2020/0058675 A1 to Liu et al. teaches (FIG. 5D) a conductive buffer (518, ¶ [0073],[0074]);
U.S. Patent Application Publication Number 2018/0182771 A1 to Costa et al. teaches (FIG. 11A-11D) forming a conductive buffer (179, ¶ [0175],[0176]);
U.S. Patent Application Publication Number 2020/0395371 A1 to Nagamoto et al. teaches a spacer film (20) which may be formed of silicon (¶ [0043]);
U.S. Patent Application Publication Number 2017/0271261 A1 to Tsutsumi et al. teaches (e.g. FIG. 11) annular spacers (172) which may be silicon (¶ [0081]);
U.S. Patent Application Publication Number 2020/0258898 A1 to Hu et al. teaches (Fig. 1) a connecting conductive buffer (120a,120b, ¶ [0037]);
U.S. Patent Application Publication Number 2019/0067324 A1 to Zhang et al. teaches (FIG. 5H to 5J) a conductive buffer (387, ¶ [0108],[0109]);
U.S. Patent Application Publication Number 2022/0359391 A1 to Jhothiraman et al. teaches (FIG. 1G) conductive buffers (115, ¶ [0042]);
U.S. Patent Application Publication Number 2017/0110473 A1 to Lee teaches (FIG. 2A,2B) conductive buffer ring patterns (RP, ¶ [0036]);
U.S. Patent Application Publication Number 2020/0303399 A1 to Xiao teaches (e.g. FIG. 1A) conductive buffer inter-deck plugs (110, ¶ [0027]);
U.S. Patent Application Publication Number 2019/0378849 A1 to Tao et al. teaches (e.g. FIG. 2Q) connection buffer (32, ¶ [0092]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891