Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US 10,141,254 B1) in view of Mae et al. (EP 3 203 625 B1).
CLAIMS 6 & 7: Xu teaches a power semiconductor package (Xu et al. teaches a "power module" (col. 3, line 23) which is a "direct bonded copper power module" (Title).) comprising:
a first substrate 52 assembly which comprises a plurality of power semiconductor dies (Xu et al. - col. 5, lines 6, 36-62 - Teaches a first DBC substrate assembly which "includes high-side transistor dies 63, 64 and high-side diode dies 65, 66);
a second substrate assembly 57 which is arranged substantially parallel to the first substrate assembly 52, the second substrate assembly comprising a copper cladding layer (Xu et al. – Fig. 5 & col. 4, lines 52-54 – “a second DBC substrate 57”) which defines a source copper cladding layer circuit which comprises a bonding area which is configured to be mechanically contacted so as to provide an electrical connection to the source copper cladding layer circuit (Xu et al. – Fig. 5 & col. 5, lines 36-62 – The etched circuit pattern defines an "output plate 61" which provides the source/emitter connection for the dies. );
and a plurality of source contacts each of which provides an electrical connection between a source connection of one of the plurality of power semiconductor dies of the first substrate assembly and the source copper cladding layer circuit of the second substrate assembly, the plurality of source contacts being arranged at different distances from the bonding area of the source copper cladding layer circuit (Xu et al. teaches emitter/source contacts 73 (Xu also refers to as “conductive spacers”) that join the emitter sides (source connections) of the dies to the circuit layer (col. 5, lines 36-62). As shown in Figs. 4-5, dies 63 and 64 (and their respective spacers/contacts 73) are arranged at different physical distances from the terminal pad/bonding area of the DBC 52.), wherein,
the source copper cladding layer circuit further comprises an electrically isolating notch (alternative to the claimed “slot”) which is arranged between a source contact of the plurality of source contacts which is closest to the bonding area of the source copper cladding layer circuit and the bonding area of the source copper cladding layer circuit (Xu et al. explicitly teaches that the "high-side plate defines a first indented notch 80/90/94 (Figs. 9-11[conceptually similar to a electrically isolating slot] disposed between the high-side transistor die [source contact] and the high-side terminal pad [bonding area]" (col. 2, lines 35-56 & col. 5, line 63 -col. 6 line 61).
While Xu et al. teaches an indented notch to "concentrate a magnetic flux" (col. 2, lines 35-56), it does not explicitly state that a “slot” is used for electrical isolation of the contacts, and may not explicit teach where the notch is arranged between a source contact of the plurality of source contacts which is closest to the bonding area of the source copper cladding layer circuit and the bonding area of the source copper cladding layer circuit.
In Xu et al. the teaching is of the manipulation of magnetic flux, which is a direct result of engineering current flow by use of a notch which is structurally similar and serving the directly analogous function of redirecting current flow through the DBC to the contacts. Noting, Xu further teaches, “A gap 98 breaks continuity around notch 97 so that Eddy currents cannot form”, further acknowledging the gap/notches “isolate” current follow in regions of the DBC (Fig. 20 & col. 5, line 63 -col. 6 line 61).
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Mae et al. teaches the explicit use of "slits" (synonymous with electrically isolating slots) provided in "conductor paths" (DBC cladding layers) specifically to act to equalize the electric current flowing in the electric current path (Mae ¶ [0014]).
It would have been obvious to a person of ordinary skill in the art (PHOSITA) to modify the indented notch of Xu et al. using the teachings of Mae et al. to ensure current uniformity flows to the contacts, by specifically using slits/slots. The motivation for this combination is that in layouts with multiple contacts at varying distances, "the path lengths of the bus bar electric currents are unequal" (Mae ¶[0019]), which leads to electric current imbalance (¶[0001-5]). By arranging the slot between the closest contact and the bonding area, the current is forced to make a “detour," (¶[0001-5] & Figs. 5 & 15) making the path lengths for all dies substantially the same (¶[0057-58]).
Regarding specific arrangement, location, and shape (Claim 7) of the slit: It is noted that the intended interpretation of the required location recited in Claim 6 may be unclear. Therefore, Claim 6 and Claim 7 are being treated together, as claim 7 further describes the slot as a U-shape around the contact. This grouping ensures a broadest reasonable interpretation (BRI) of the “location” and “arrangement” feature based on the provided dependent structural details.
To the extent that Xu et al. or Mae et al. do not explicitly recite the specific geometry of the slot (such as a U-shape surrounding the contact such that the slot “is arranged between a source contact of the plurality of source contacts which is closest to the bonding area (bonding “area” is ambiguous not explicitly defining a exact location, thus open to BRI.) of the source copper cladding layer circuit and the bonding area of the source copper cladding layer circuit”), such a configuration is a matter of routine design choice under guidance of MPEP § 2144.04.
A PHOSITA, seeking to implement the "detour" path taught by Mae et al. within the package of Xu et al., would recognize that the specific shape and perimeter of the slot are variable parameters. The selection of a specific shape (e.g., U-shaped or encircling) to surround a contact, in order to direct current in a desirable path, is merely the selection of an optimal configuration from a limited number of predictable geometric shapes to achieve the known result of path equalization. Without such a configuration, heat generation occurs in a concentrated manner and this is likely to degrade solder and by redistributing current flow, “heat generation concentration can be prevented, and the reliability of the electric power conversion apparatus can be improved” (Mae ¶[0003, 15]). Therefore, the modification represents the predictable application of known prior art elements to achieve an improved and expected result.
Claim 8 Xu et al. in view of Mae et al. teaches a power semiconductor package as recited in claim 6, wherein the electrically isolating slot is arranged to surround at least two source contacts of the plurality of source contacts (Xu as modified/optimized in view of the teachings presented in Mae).
Claim 9 Xu et al. in view of Mae et al. teaches a power semiconductor package as recited in claim 6, wherein the electrically isolating slot is configured so that so that a ratio of a maximum peak turn-on current to a minimum peak turn-on current of the plurality of power semiconductor dies does not exceed 1.1 (Mae et al. ¶[0029] teaches that slots make "magnitudes of the switching module electric currents... into substantially the same magnitude" and that current distribution... is equalized. This would be expected to be a ratio of 1 is the ideal optimization.).
Claim 10 Xu et al. in view of Mae et al. teaches a power semiconductor package as recited in claim 6, wherein the source copper cladding layer circuit further comprises at least one additional electrically isolating slot (Xu Fig. 13 & Mae fig. 5 0- Mae demonstrates various example including multiple slits/slots. )
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Claim 11 Xu et al. in view of Mae et al. teaches a power semiconductor package as recited in claim 10, wherein the electrically isolating slot and the at least one additional electrically isolating slot are configured so that a ratio of a maximum peak turn-on current to a minimum peak turn-on current of the plurality of power semiconductor dies does not exceed 1.1 (Mae et al. ¶[0029] teaches that slots make "magnitudes of the switching module electric currents... into substantially the same magnitude" and that current distribution... is equalized. This would be expected to be a ratio of 1 is the ideal optimization.).
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
3/5/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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