Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/28/2026 have been fully considered but they are not persuasive.
Regarding the augment to the rejection of claim 6 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, that is supported by the specification is unpersuasive.
The specification describes the oxide layer (e.g., SiO2) as an interfacial layer formed directly on a semiconductor substrate/channel (e.g., Si) within a MOS gate stack structure. There is no disclosure or written description support in the specification as filed for disposing a bottom metal layer directly beneath this oxide layer, nor for a "metal-oxide-metal" configuration that incorporates such an interfacial oxide layer within the gate stack. While the specification illustrates metal-insulator-metal (MIM) capacitor test structures in Figures 2B, 3C, 7B, and 7C, these configurations place the superlattice layer directly between metal electrodes without an intervening oxide layer. Accordingly, the subject matter of claim 6 lacks written description support under 35 U.S.C. 112(a).
The applicant's argument that claim 6 is supported by the specification is unpersuasive because the specification describes the interfacial oxide layer strictly as being formed directly on a semiconductor substrate or channel within a metal-oxide-semiconductor gate stack structure. There is no written description support in the original filing for disposing a bottom metal layer directly beneath this oxide layer to form a metal-oxide-metal configuration. While metal-insulator-metal structures are illustrated in the drawings, those test configurations place the superlattice layer directly between metal contacts without an intervening oxide layer. Consequently, claim 6 lacks written description support under 35 U.S.C. 112(a).
Regarding the nonobviousness arguments for claims 14 through 16 and 19, the combination of Yoo and Mears remains proper under 35 U.S.C. 103. A PHOSITA seeking to construct a functional field-effect transistor would naturally look to combine Yoo's high-k gate stack structure with Mears' conventional source and drain regions and contacts. Relying on Mears to provide standard input and output contact structures represents a routine application of known techniques to an analogous device to achieve a predictable result under KSR.
Regarding claim 20, the applicant's assertion that the claimed transconductance range is nonobvious due to unrecited processing steps is unpersuasive. Claim 20 is a apparatus claim directed to a physical device structure, not a method of manufacture defined by specific atomic layer deposition cycling or annealing conditions. Because the structural combination of Yoo and Mears provides the identical physical gate stack and channel configuration, the resulting intrinsic transconductance of 1.7 to 1.8 µS/µm is an inherent physical property that naturally flows from that combined structure under In re Best.
Finally, the arguments regarding claims 3, 4, 17, and 18 fail to overcome the rejection over Yoo, Mears, and Cartier. Cartier explicitly teaches interfacial oxide layers within a standard range of 0.1 nm to 1.5 nm, which directly encompasses the applicant's claimed physical range of 8 to 8.5 Å. Because interfacial oxide thickness is a well-established result-effective variable for tuning equivalent oxide thickness and device performance, selecting a specific sub-range within the prior art teaching constitutes routine optimization under In re Applied Materials and In re Aller. Moreover, attorney argument asserting unexpected results cannot take the place of comparative experimental data against the closest prior art.
For these reasons the rejections of the claim are maintained and made FINAL.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 is rejected as being inaccurate and improperly defined. The claim specifies a "a gate stack… comprising… a bottom metal layer disposed beneath the oxide layer, thereby forming a metal-oxide-metal capacitor configuration" but describes a structure comprising a "the metal layer [e.g. gate] disposed over the oxide layer" within a "gate stack". In the context of a gate stack, the material beneath the oxide layer is a semiconductor (semiconductor channel), not a metal layer. Therefore, the resulting structure is a Metal-Oxide-Semiconductor (MOS) capacitor or Metal-Insulator-Semiconductor (MIS) capacitor, not a Metal-Insulator-Metal (MIM) structure as claimed. The use of the phrase "metal-oxide-metal" is technically inaccurate based on the materials described, failing to distinctly point out the subject matter of the invention.
Claim 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification describes the oxide layer (e.g., SiO_2, element 26) strictly as an interfacial layer formed directly on a semiconductor substrate/channel (e.g., Si, element 16) within a MOS gate stack structure. There is no disclosure or written description support in the specification as filed for disposing a bottom metal layer directly beneath this oxide layer, nor for a "metal-oxide-metal" configuration that incorporates such an interfacial oxide layer within the gate stack. While the specification illustrates metal-insulator-metal (MIM) capacitor test structures in Figures 2B, 3C, 7B, and 7C, these configurations place the superlattice layer directly between metal electrodes without an intervening oxide layer.
Further, the specification describes the interfacial oxide layer strictly as being formed directly on a semiconductor substrate or channel within a metal-oxide-semiconductor gate stack structure. There is no written description support in the original filing for disposing a bottom metal layer directly beneath this oxide layer to form a metal-oxide-metal configuration. While metal-insulator-metal structures are illustrated in the drawings, those test configurations place the superlattice layer directly between metal contacts without an intervening oxide layer. Consequently, claim 6 lacks written description support under 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo (US 20180240804 A1).
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CLAIM 1. Yoo teaches a gate stack (Fig. 1) comprising:
an oxide layer 125a disposed over a semiconductor substrate 101; and
a periodic sequence of (HfO2 125 -ZrO2 135)xN material layers disposed over the oxide 115 layer, wherein N is a natural counting number (Fig. 1).
CLAIM 2. Yoo teaches a gate stack of claim 1 wherein the oxide layer 115 comprises silicon dioxide (Yoo - ¶21).
CLAIM 5. Yoo teaches a gate stack of claim 1 further comprising a metal layer (¶31-32) disposed over the periodic sequence of (HfO2-ZrO2)xN material layers (Yoo Fig. 1).
CLAIM 6. Yoo teaches a gate stack of claim 5 further comprising the metal layer disposed over the oxide layer in a metal-oxide-metal capacitor configuration (If a semiconductor channel is consider a “metal” is considered a “metal” as required by the claim, then the structure of Yoo Fig. 1 meets the scope of the claim.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 20180240804 A1) in view of Mears et al. (US 20060019454 A1).
CLAIM 14. Yoo in view of Mears teach semiconductor device comprising: a semiconductor substrate 101 having a source region 102, a channel region 101 spaced from the source region and a drain region 103 spaced from both the source region and channel region;
a gate stack 155 comprising: an oxide layer disposed over the channel region 101;
a periodic sequence of (HfO2-ZrO2)xN material layers disposed over the oxide layer , wherein N is a natural counting number; and a gate contact 155 disposed over the periodic sequence of (HfO2-ZrO2)xN material layers (Yoo Fig. 1).
The omission of explicitly illustrated source/drain contacts in Yoo does not constitute a deficiency in the teaching; rather, such contacts are standard, necessary components for input/output functionality in transistor structures. Mears serves as a proper basis for modification by expressly disclosing an analogous transistor structure (Fig. 1) utilizing \(HfO_2/ZrO_2\) insulating regions, while further teaching the explicit inclusion of conventional source/drain contacts (30, 31). A POSITA, seeking to finalize the device for practical application, would have looked to Mears to provide these contacts. This modification represents the application of a known technique to a known device to achieve a predictable result, which is deemed obvious under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385.
CLAIM 15. Yoo in view of Mears teach semiconductor device (10) of claim 14 wherein the semiconductor substrate comprises silicon (Yoo ¶19).
CLAIM 16. Yoo in view of Mears teach semiconductor device of claim 14 wherein the oxide layer comprises silicon dioxide (Yoo ¶21).
CLAIM 19. Yoo in view of Mears teach semiconductor device of claim 14 wherein the source contact , the drain contact and the gate contact comprise metal (Mears ¶70- contacts are silicide comprising Ti for example.) .
CLAIM 20. Yoo in view of Mears teach semiconductor device of claim 14, however may be having an intrinsic transconductance of between 1.7 uS/um and 1.8 uS/um. While the prior art references may not explicitly recite this specific range, the combination of Yoo and Mears explicitly teaches the necessary structural components as required by the claim that necessarily result in the claimed transconductance value. It is well-established that if a prior art structure is the same as the claimed structure, it can be assumed the device will inherently perform the claimed properties, including specific electrical characteristics. Therefore, since the combined prior art teaches the same structure, the same properties would be a obvious expectation by a PHOSITA.
Claim(s) 17-18 and 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo (US 20180240804 A1) in view of Mears et al. (US 20060019454 A1) in view of Cartier et al. (US 20060246740 A1).
CLAIM 17 & 3. Yoo in view of Mears teach a semiconductor device of claim 16 & 2, however is silent upon wherein the [interfacial] oxide layer 115 is between 8 Ang and 8.5 Ang in thickness. While Yoo does not explicitly recite a numerical range, Yoo explicitly identifies the layer as an 'interfacial' oxide. A person having ordinary skill in the art (PHOSITA) would understand from Cartier (¶ 36) that such interfacial layers possess a known, standard thickness range of 0.1 nm to 1.5 nm. Placing the claimed range directly within this established, effective range makes the selection an obvious design choice. Furthermore, the thickness of this interfacial layer is a result-effective variable, optimized for high-k gate dielectric performance. Discovering the optimum value within this narrow, known range constitutes routine experimentation, not invention. See MPEP § 2144.05; In re Applied Materials, Inc., 692 F.3d 1289 (Fed. Cir. 2012).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 18 & 3. Yoo in view of Mears teach a semiconductor device of claims 16 & 2, however is silent upon wherein the oxide layer 115 has an effective thickness between 5.5 Ang and 6.5 Ang. While Yoo does not explicitly recite a numerical range, Yoo explicitly identifies the layer as an 'interfacial' oxide. A person having ordinary skill in the art (PHOSITA) would understand from Cartier (¶ 361) that such interfacial layers possess a known, standard thickness range of 0.1 nm to 1.5 nm. Placing the claimed range directly within this established, effective range makes the selection an obvious design choice. Furthermore, the thickness of this interfacial layer is a result-effective variable, optimized for high-k gate dielectric performance. Discovering the optimum value within this narrow, known range constitutes routine experimentation, not invention. See MPEP § 2144.05; In re Applied Materials, Inc., 692 F.3d 1289 (Fed. Cir. 2012).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/4/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Cartier - [0036] In some embodiments of the present invention (not shown herein), an interfacial layer comprising SiO.sub.2 or SiON having a thickness from about 0.1 to about 1.5 nm is formed on the surface 13 of the substrate 12 prior to forming the gate dielectric 22. The optional interfacial layer is formed by one of the above mentioned techniques that were used in forming the gate dielectric, i.e., CVD, PECVD, ALD and the like. Thermal oxidation or chemical oxidation may also be used.
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