DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 7 is objected to because of the following informalities: claim 7 is dependent from itself. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: please change “clam” to “claim”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kotlyar et al. (U.S. Patent No. 8,890,120) in view of Lin et al. (U.S. Patent No. 11,139,379).
Regarding to claim 1, Kotlyar teaches a semiconductor element comprising:
an element structure of a tunnel field-effect transistor (Fig. 2B, element structure including channel 206B, Source 208B, Drain 210B, and Gate 212B); and
a channel part formed of an indirect transition-type semiconductor (Fig. 2B, element 206B, column 5, line 52, column 3, lines 60-63), which is configured to have a plate-like shaped portion having one end connected to a source part and the other end connected to a drain part (Fig. 2B, column 5, lines 53-54, channel part 206B has plate-like shaped portion, one end connected to source part 208B and the other end connected to drain part 210B);
wherein, of two pairs of opposing surfaces of first opposing surfaces and second opposing surfaces which constitute the plate-like shaped portion and are opposed in a direction perpendicular to the direction in which a current flows from the source part to the drain part (Fig. 2B, the direction in which current flows from the source part to the drain part is left to right direction in the figure; the first surface of the first pair is the front surface of element 206B, the second surface of the first pair is the back surface of element 206B; the first surface of the second pair the top surface of element 206B, the second surface of the second pair is the bottom surface of element 206B), at least one pair of the opposing surfaces selected from the two pairs is formed by arranging at a facing interval between the opposing surfaces (the first surface of the one pair is the front surface of element 206B, the second surface of the one pair is the back surface of element 206B), electron confinement surfaces in which a band structure of a direct transition-type semiconductor is capable of being simulatively given to the indirect transition-type semiconductor by regulation of electron motion (column 9, lines 38-46).
Kotlyar is silent about the dimension of facing interval between the opposing surfaces.
Lin discloses at least one pair of the opposing surfaces selected from the two pairs is formed by arranging at a facing interval of 15 nm at the longest between the opposing surfaces (column 20, lines 42-45, the opposing surfaces is formed by arranging at a facing interval of 10 nm at the longest between the opposing surfaces of the fin). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kotlyar in view of Lin to configure the interval to be 15 nm or less in order to reduce footprint of the device.
Regarding to claim 2, Kotlyar teaches all of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces are constituted of the electron confinement surfaces (Fig. 2B, column 4, lines 24-28).
Regarding to claim 4, Kotlyar teaches the indirect transition-type semiconductor is silicon, and the electron confinement surface is a {100} plane (column 6, lines 62-65).
Regarding to claim 5, Kotlyar teaches the indirect transition-type semiconductor is germanium, and the electron confinement surface is a {111} plane (column 6, lines 62-65).
Regarding to claim 7, Kotlyar teaches a tunnel junction formed in the tunnel field-effect transistor is constituted of a semiconductor junction (column 14, lines 62-66).
Regarding to claim 8, Kotlyar teaches the tunnel junction formed in the tunnel field-effect transistor is constituted of a Schottky junction (column 11, lines35-40, the tunnel junction formed in the tunnel field-effect transistor is constituted of a Schottky junction, which is metal and semiconductor junction).
Regarding to claim 9, Kotlyar teaches a semiconductor integrated circuit comprising the semiconductor element according to claim 1 (column 14, lines 27-32).
Regarding to claim 10, Kotlyar as modified discloses a method for manufacturing the semiconductor element according to claim 1, comprising: a channel part forming step of forming by an indirect transition-type semiconductor (Fig. 2B, element 206A, column 5, line 52, column 3, lines 60-61), a channel part having a plate-like shaped portion having one end connected to a source part and the other end connected to a drain part (Fig. 2B, column 5, lines 53-54, channel part 206B have plate-like shaped portion, one end connected to a source part 208B and the other end connected to a drain part 210B), and forming, of two pairs of opposing surfaces of first opposing surfaces and second opposing surfaces which constitute the plate-like shaped portion and are opposed in a direction perpendicular to the direction in which a current flows from the source part to the drain part (the first surface of the one pair the front surface of element 206B, the second surface of the one pair is the back surface of element 206B), at least one pair of the opposing surfaces selected from the two pairs by arranging at a facing interval of 15 nm at the longest between the opposing surface (Kotlyar as modified in view of Lin results in this feature), electron confinement surfaces in which a band structure of a direct transition-type semiconductor is capable of being simulatively given to the indirect transition-type semiconductor by regulation of electron motion (column 9, lines 40-46).
Examiner’s note: Claim 10 is a method claim, while claim 1, which claim 10 is dependent from, recites a structure. Therefore, the recitation is a product-by-process recitation. The primary prior art is construed herein as teaching the structural features as claimed. If the methods of forming the layers are different, the process must result in a structural difference over the prior of record herein. The patentability does not depend on its method of production unless the method results in a distinct structure. A product by process claim is a product. Determination of patentability is based on the product itself. If the product claimed is the same as or obvious from a product of the prior art, the claim in unpatentable even though the prior product was made by a different process. Once a product is found appearing to be substantially identical and a rejection over the art is made, the burden shifts to the applicant to show an unobvious difference.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kotlyar et al. (U.S. Patent No. 8,890,120) and Lin et al. (U.S. Patent No. 11,139,379), as applied to claim 1, above, further in view of Yang et al. (U.S. Patent No. 10,600,881).
Regarding to claim 3, Kotlyar discloses a gate part constituting the element structure of the tunnel field-effect transistor is arranged to cover part of four constituent surfaces constituting the first opposing surfaces (Fig. 2B, element 212B, column 6, lines 20-23). Kotlyar as modified does not disclose a gate part constituting the element structure of the tunnel field-effect transistor is arranged to cover all or part of at most three of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces. Yang discloses a gate part constituting the element structure of the tunnel field-effect transistor is arranged to cover all or part of at most three of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces (Fig. 1, gate part 140 constituting the element structure of the tunnel field-effect transistor is arranged to cover all of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kotlyar in view of Yang to arrange a gate part constituting the element structure of the tunnel field-effect transistor to cover all or part of at most three of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces in order to increase channel width, thus to boost performance due to a higher switching speed.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 6, the prior art fails to anticipate or render obvious the claimed limitations including “wherein the indirect transition-type semiconductor is a mixed crystal of silicon and germanium, when the content of the germanium is less than 85 atomic%, the electron confinement surface is a {100} plane, and when the content of the germanium is 85 atomic % or more, the electron confinement surface is a {111} plane” in combination with the limitations recited in claim 1.
Pertinent Art
For the benefits of the Applicant, US-10249744-B2, US-12382843-B2, US-8173993-B2, and US-9613955-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. In particular, these references fail to disclose “at least one pair of the opposing surfaces selected from the two pairs is formed by arranging at a facing interval of 15 nm at the longest between the opposing surfaces, electron confinement surfaces in which a band structure of a direct transition-type semiconductor is capable of being simulatively given to the indirect transition-type semiconductor by regulation of electron motion.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897