DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP 2011124366A (‘366) and further in view of JP 2009176825 (‘825).
Pertaining to claim 1, ‘366 teaches a semiconductor device comprising:
a first wiring layer in which a first wiring is formed See Figure 4 marked up below;
a first semiconductor chip 55 mounted on the first wiring layer See Figure 4 marked up below;
a second wiring layer that is disposed on the first wiring layer and in which a second wiring is formed See Figure 4 marked up below;
a second semiconductor chip 68 mounted on the second wiring layer See Figure 4 marked up below;
a through-hole formed in the second wiring layer See Figure 4 marked up below;
a molding resin layer 56 [0059] that molds the first semiconductor chip on the first wiring layer and a molding resin layer 56 that molds the second semiconductor chip on the second wiring layer See Figure 4 marked up below note that both molding layers are the same material (both element 56); and
a through electrode 65 that is formed to penetrate the molding resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring to each other See Figure 4 marked up below.
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The ‘366 reference fails to teach the molding layers being integrally formed through a through-hole. The ‘825 reference teaches a molding layer integrally formed through a through-hole in a wiring layer to mold above and below the wiring layer (note that a through hole other than what is demarked above can be added to the wiring layer to effect the process as taught by ‘825 and that the molding material of ‘366 is the same for both layers) See Figure 2A and 2B below. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate a molding process through a through-hole to mold above and below a wiring layer such as the process taught by ‘825 see [0030-0034]. The reason one of ordinary skill in the art would want to use this process for molding would be to anchor the top and bottom molding layers to reduce the possibility of peeling [0034] as the two sides are anchored to each other through the through-hole.
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Pertaining to claim 2, the ‘366 reference teaches the semiconductor device according to claim 1, wherein the first semiconductor chip 55 [0064] and the second semiconductor chip 68 [0073] respectively include materials different from each other. ‘366 teaches that 55 and 68 are different types of chips, 55 is a low pass filters and 68 is a surface acoustic wave filter.
Allowable Subject Matter
Claims 3-4 are allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitations:
With respect to claim 3: the prior art does not teach nor suggest a second step of forming, on the first wiring layer, an auxiliary substrate including an opening in a formation region of the first wiring; a third step of mounting a first semiconductor chip on the first wiring layer in the opening of the auxiliary substrate; a fourth step of forming, on a second support substrate, a second wiring layer in which a second wiring is formed and a through-hole that penetrates the second support substrate is formed outside a formation region of the second wiring, in conjunction with the specific order of steps as claimed.
With respect to claim 4: the prior art does not teach nor suggest a fourth step of forming, on a second support substrate, a second wiring layer in which a second wiring is formed; a fifth step of mounting a second semiconductor chip on the second wiring layer; a sixth step of forming a second insulating layer that covers the second semiconductor chip on the second wiring layer; a seventh step of removing the second support substrate from the second wiring layer on which the second semiconductor chip covered with the second insulating layer is mounted; an eighth step of disposing, on the first insulating layer, the second wiring layer from which the second support substrate is removed; and a ninth step of forming a through electrode that penetrates the first insulating layer and connects the first wiring and the second wiring to each other in conjunction with the specific order of steps as claimed.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817