DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-12 in the reply filed on January 9, 2026 is acknowledged.
However, amended claim 12 is directed to then non-elected invention Group I, and is hereby withdrawn. Claims 1-11 will be examined in the instant application, as elected (invention Group II).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/15/2026, 09/19/2025, 01/15/2025, and 10/05/2023 are being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the abstract contains more than 150 words and is more than one paragraph.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 2 recites the broad recitation “implantation energy of less than 10 keV”, and the claim also recites "in particular at or below 5 keV" which is the narrower statement of the range/limitation. The claim is considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claim.
For examination purpose, the claim limitation will be examined for an implantation energy of less than 10 keV.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 2009/0057759 A1) in view of Bartsch et al. (US 2001/0023124 A1).
Regarding claim 1, Obradovic et al. teaches a method for forming an ohmic contact (silicides 190) on a semiconductor device (substrate 20), comprising:
shallow implanting (XSD 95 and 98) a dopant ([0044]) through a first surface of the semiconductor device (top surface side, substrate 20) using an implantation energy of less than 15 keV ([0039]) to form at least one interface region (source drain extensions 90) in a semiconductor material;
rapid thermal processing of the at least one interface region comprising the implanted dopant at a temperature below 1100C ([0045]);
after rapid thermal processing of the at least one interface region, depositing a metal material on top of the at least one interface region (metal deposition, [0049]) to form at least one ohmic contact region (silicided regions 190); and
optionally annealing the deposited metal material at an annealing temperature below 700C ([0051]).
Obradovic et al. is silent to forming an ohmic contact on a wide-bandgap semiconductor device. However, Obradovic et al. teaches engineering bandgap for application specific semiconductor devices ([0021]).
Bartsch et al. teaches forming an ohmic contact (source drain electrodes 209 and 210) on a wide-bandgap semiconductor device (SiC basic body 200). Bartsch et al. further teaches that SiC provides for high breakdown field strength suitable for power electronics ([0005]).
It would have been obvious to one of ordinary skill in the art before the effective filing date, to form the semiconductor device of Obradovic et al. to the wide-bandgap semiconductor device of Bartsch et al.. Forming an ohmic contact on a wide-bandgap semiconductor device would allow for low resistance contact suitable for use in power electronics (Bartsch et al., [0005]).
Regarding claim 2, as best understood based on the 35 U.S.C. 112(b) issue identified above, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches wherein shallow implanting is performed with an implantation energy of less than 10 keV ([0039]).
Regarding claim 3, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches wherein rapid thermal processing is performed at a temperature of 1000C and/or for a duration of five minutes. Obradovic et al. ([0045]).
Regarding claim 4, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches wherein the deposited metal material is annealed at an annealing temperature of 450C, 550C, or 700C. Obradovic et al. ([0051]).
Regarding claim 5, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches wherein shallow implanting the dopant comprises implanting the dopant into the wide-bandgap semiconductor material using a dose between 10.sup.14 cm.sup.-2 and 10.sup.18 cm.sup.-2 . Obradovic et al. ([0042]).
Regarding claim 6, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradbovic et al. teaches the method of Claim 1, wherein the first surface corresponds to a top surface (FIG. 2, top surface side, substrate 20) of the wide-bandgap semiconductor device and
the metal material is deposited on top of the at least one interface region to form the at least one ohmic contact region on the frontside (FIG. 1, silicide layer 190) of the wide-bandgap semiconductor device.
Regarding claim 7, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches wherein, after forming the interface region, further processing steps ([0045], source/drain anneal step) are carried out for forming specific wide-bandgap semiconductor devices.
Regarding claim 8, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches further comprising:
forming an oxide layer ([0047] deposition of the oxide layer 152) before depositing the metal material.
Regarding Claim 10, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches further comprising:
forming at least one trench structure ([0026], shallow trench isolation structures 50 formed within NMOS and PMOS regions 30, 40) within the wide-bandgap semiconductor material; and
using the at least one trench structure to laterally self-align the at least one interface region and the at least one ohmic contact region (FIG. 1).
Regarding Claim 11, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1. Obradovic et al. teaches further comprising:
etching the wide-bandgap semiconductor material to form at least one recess, wherein the at least one ohmic contact region formed on a third surface of the at least one contact region serves as an etching mask ([0036], sidewall spacers layers 142 and 144 are anisotropically etched, leaving remaining spacers to act with photoresist as implantation template for the source/drain regions).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. in view of Bartsch et al. and Slater et al. (US 2005/0104072 A1).
Regarding claim 9, Obradovic et al. in view of Bartsch et al. teaches the method of claim 1, but fails to teach further comprising forming at least one backside contact on a second surface of the semiconductor device, wherein forming the at least one backside contact includes an annealing step, which results in the thermal treatment of the interface region.
However, Slater et al. teaches further comprising forming at least one backside contact on a second surface of the semiconductor device ([0056], a metal layer 110 is formed on a back side of the SiC substrate 105 opposite the epitaxial layer 100), wherein forming the at least one backside contact includes an annealing step ([0055], metal-silicon carbide ohmic contacts formed by annealing the interface locations on the substrate using laser light), which results in the thermal treatment of the interface region.
Slater et al. is considered to be analogous art because it is reasonably pertinent to the field of forming ohmic contact. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method as taught by the combination of Obradovic et al. in view of Bartsch et al. to incorporate the teachings of Slater to include forming metal-silicon carbide ohmic contact layer on the backside of a semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898