DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/15/2026, 09/19/2025, 01/15/2025, and 10/05/2023 are being considered by the examiner.
Claim Objections
Claim 11 objected to because of the following informalities:
The limitation "the at least one contact region" is inconsistent with previously recited "the at least one ohmic contact region", or else lacks antecedent basis. For examination purposes, to be understood as “the at least one ohmic contact region”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 4 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The annealing temperature choice of "700°C" in the limitation "450°C, 550°C or 700°C" of claim 4 is not "below 700°C", as required by its independent claim 1 above.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Response to Amendment
The Amendment filed 5/20/2026 has been entered. Claims 1-13 and 26-37 remain pending in the application. Applicant’s amendments to the Specification and Claims have overcome, respectively, each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed 04/07/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8,10, 11, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1) and Slater, JR. (US 20020179910 A1).
Regarding claim 1, Obradovic et al. teaches method for forming an ohmic contact (silicides 190) on a wide- bandgap semiconductor device (CMOS device), the method comprising:
shallow implanting a dopant ([0044], XSD 95 and 98) through a first surface (FIG.2, top surface side) of the wide-bandgap semiconductor device using an implantation energy of less than 15 keV ([0039]) to form at least one interface region (source/drain extensions 90) in a wide-bandgap semiconductor material (semiconductor wafer 10);
rapid thermal processing ([0046], CW laser anneal with additional flash RTA) of the at least one interface region comprising the implanted dopant ([0029], n-type dopant from XSD implant) at a temperature below 1100°C ([0045]);
after rapid thermal processing of the at least one interface region, depositing a metal material on top of the at least one interface region ([0050]) to form at least one ohmic contact region (silicided regions 190), and
annealing the deposited metal material ([0051]) at an annealing temperature (450°C) below 7000C.
Obradovic et al. is silent to forming an ohmic contact on a wide-bandgap semiconductor device but does teach engineering bandgap for application specific semiconductor devices ([0021]).
Bartsch et al. teaches forming an ohmic contact (source electrode 209 and drain electrode 210) on a wide-bandgap semiconductor device (SiC basic body 200). Bartsch et al. further teaches that SiC provides for high breakdown field strength suitable for power electronics ([0005]).
Obradovic et al. in view of Bartsch et al. does not expressly teach wherein the deposited metal material forms at least one contact metal layer without chemically reacting with the wide-bandgap semiconductor material in the at least one interface region, and wherein the at least one ohmic contact region comprises more than 99% metal material.
However, Slater, JR. teaches wherein the deposited metal material ([0034] and FIG.1) forms at least one contact metal layer (contact metal 18) without chemically reacting ([0033], nonreactive contact metal, and [0047], not interact adversely with substrate) with the wide-bandgap semiconductor material ([0033], SiC substrate 12) in the at least one interface region (interface 20), and wherein the at least one ohmic contact region (understood to include, unless otherwise expressly stated, deposited contact metal layer separately from SiC interface region, and thus deposited contact metal layer (18) accordingly corresponds to claimed ohmic contact region) comprises more than 99% metal material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the deposited contact layer of Slater, JR. as the ohmic contact of the method of Obradovic et al. in view of Bartsch et al. and thus correspond to an ohmic contact comprising 99% metal, as best understood under broadest reasonable interpretation as separate from underlying SiC interface, unless expressly stated otherwise. Using the nonreactive contact metal of Slater, JR. in the method of Obradovic et al. in view of Bartsch et al. would prevent adverse interaction between contact metal and semiconductor material, thereby ensuring minimal interface resistance and avoiding degradation of ohmic contact performance.
Regarding claim 2, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein shallow implanting ([0044], XSD 95 and 98) is performed with an implantation energy of less than 10 keV ([0039]).
Regarding claim 3, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein rapid thermal processing ([0046], CW laser anneal with additional flash RTA) is performed at a temperature of 10000C ([0045]).
Regarding claim 4, as best understood based on the 35 U.S.C. 112(d) issue identified above, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein the deposited metal material ([0050]) is annealed at an annealing temperature of 450°C ([0051]).
Regarding claim 5, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein shallow implanting the dopant ([0044], XSD 95 and 98) comprises implanting the dopant ([0029], n-type dopant from XSD implant) into the wide-bandgap semiconductor material (semiconductor wafer 10) using a dose ([0042]) between 1014/cm2 and 1018/cm2.
Regarding claim 6, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein the first surface (FIG.2, top surface side) corresponds to a top surface of the wide-bandgap semiconductor device (CMOS device) and the metal material is deposited on top of the at least one interface region ([0050]) to form the at least one ohmic contact region (silicided regions 190) on a front side (FIG.1) of the wide-bandgap semiconductor device (CMOS device).
Regarding claim 7, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein, after forming the interface region (source/drain extensions 90), further processing steps ([0046], various processes for annealing step) are carried out for forming specific wide-bandgap semiconductor devices ([0060], non-MOS devices, e.g. bipolars, JFETs, inductors, capacitors).
Regarding claim 8, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein further comprising forming ([0047]) an oxide layer (152) before depositing the metal material ([0050]).
Regarding claim 10, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches further comprising: forming at least one trench structure ([0026], shallow trench isolation structures 50) within the wide-bandgap semiconductor material (semiconductor wafer 10); and using the at least one trench structure to laterally self-align ([0038]) the at least one ohmic contact region (outer edges of the deep source/drain sidewall spacers 142, 144 of silicided regions 190).
Regarding claim 11, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches further comprising: etching ([0054], anisotropic etch) the wide-bandgap semiconductor material (semiconductor wafer 10) to form at least one recess (contact holes), wherein a frontside electrode layer (doped gate polysilicon electrode 110) formed on a third surface (surface of gate dielectric 100) of the at least one contact region serves as an etching mask ([0030]).
Regarding claim 26, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. teaches wherein the metal material comprises nickel ([0051]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Slater, JR. et al. (US 20050104072 A1).
Regarding claim 9, Obradovic et al. in view of Bartsch et al. and Slater, JR. et al. teaches the method of claim 1. Obradovic et al. does not teach further comprising at least one of the following: performing a backside processing of the wide-bandgap semiconductor device, wherein the backside processing includes a thermal treatment step, which results in the thermal treatment of the interface region; or forming at least one backside contact on a second surface of the semiconductor device, wherein forming the at least one backside contact includes an annealing step, which results in the thermal treatment of the interface region.
However, Slater, JR. et al. teaches further comprising forming at least one backside contact ([0056], metal layer 110) on a second surface (surface of SiC substrate 105 opposite the epitaxial layer 100) of the semiconductor device (light emitting device), wherein forming the at least one backside contact includes an annealing step ([0058]), which results in the thermal treatment ([0058], laser light 225 heating the metal) of the interface region (FIG. 3, interface locations 330).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor-contact process of Obradovic et al. in view of Bartsch et al. and Slater, JR. to form backside contact and annealing technique taught by Slater, JR. et al. because such formation and annealing technique is known technique for forming ohmic contact. Anneal step lowers initially formed Schottky barrier and ensures low resistance current paths, thereby improving electrical performance and reliability without damaging front side.
Claims 27, 29, 30, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Tsuchiya et al. (US 20130062624 A1).
Regarding claim 27, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the metal material comprises titanium carbide.
However, Tsuchiya et al. teaches wherein the metal material (cap layer) comprises titanium carbide ([0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied titanium carbide as the metal material taught by Tsuchiya et al. in modification of the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. because Tsuchiya et al. demonstrates titanium carbide as a known contact material for semiconductor devices and would therefore have allowed a simple substitution yielding lower contact resistivity and thermal stability for ohmic contact formation.
Regarding claim 29, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the at least one ohmic contact region has a thickness of 100 nm.
However, Tsuchiya et al. teaches wherein the at least one ohmic contact region (thick nickel silicide film 18) has a thickness of 100 nm ([0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have selected the thickness of 100 nm as taught by Tsuchiya et al. in modification of the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. as a way of routine optimization to reduce barrier height and contact resistance while maintaining stability and electrical connectivity for optimal device performance.
Regarding claim 30, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the at least one ohmic contact region formed by the deposited metal material is thicker than the at least one interface region.
However, Tsuchiya et al. teaches wherein the at least one ohmic contact (thick nickel silicide film 18) region formed by the deposited metal material is thicker ([0047]) than the at least one interface region (sheet resistance layer of first layer 18a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the ohmic contact thicker than the interface as taught by Tsuchiya et al. in modification of the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. in order to overcome Schottky barrier with heavy doping of semiconductor region, yielding lower contact resistivity and contact layer less prone to degradation from oxidation or contamination.
Regarding claim 33, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach further comprising forming a frontside structure on the first surface, wherein the frontside structure comprises a metal gate and a gate insulation, the gate insulation comprising a vertical insulation area arranged on at least one side surface of the metal gate, the vertical insulation area arranged laterally between the metal gate and the at least one ohmic contact region.
However, Tsuchiya et al. teaches further comprising forming a frontside structure on the first surface, wherein the frontside structure comprises a metal gate (gate electrode 22) and a gate insulation (gate insulating film 20), the gate insulation comprising a vertical insulation area (layer insulating film 24) arranged on at least one side surface (FIG.1) of the metal gate, the vertical insulation area arranged laterally between (FIG.1) the metal gate and the at least one ohmic contact region (first nickel silicide region 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included frontside gate and insulation structure of Tsuchiya et al. to the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. as such structures are known configurations for semiconductor devices with ohmic source/drain contacts and thus improves scalability, reduces thermal stress on device, and supports later-stage frontside processing.
Claims 34 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Kobayashi et al. (JP 2019102556 A).
Regarding claim 34, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the wide-bandgap semiconductor device has a cell pitch in a range from 1.5 μm to 3 μm.
However, Kobayashi et al. teaches wherein the wide-bandgap semiconductor device (silicon carbide semiconductor device) has a cell pitch (FIG. 1, X) in a range from 1.5 μm to 3 μm ([0039], 2.0-3.0 micrometers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. to provide a cell pitch dimension taught by Kobayashi et al. within the claimed range because Kobayashi et al. demonstrates the range within the claimed range as suitable for SiC devices, thereby yielding high-density power devices with narrow cell pitches.
Regarding claim 35, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the wide-bandgap semiconductor device comprises a plurality of source and gate regions, and widths of corresponding source and gate contacts range from 0.75 μm to 1.5 μm.
However, Kobayashi et al. teaches wherein the wide-bandgap semiconductor device (silicon carbide semiconductor device) comprises a plurality of source and gate regions (FIG. 6), and widths of corresponding source and gate contacts range from 0.75 μm to 1.5 μm ([0039] and FIG. 1, 0.8-1.8 micrometers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have selected a contact width as taught by Kobayashi et al. within the overlapping portion of the claimed range in modification of Obradovic et al. in view of Bartsch et al. and Slater, JR., as this would have been a matter of routine optimization of device dimensions for performance and packing density.
Claims 32 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Cheng (US 8338255 B2).
Regarding claim 32, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 10. Obradovic et al. does not teach wherein the at least one trench structure comprises a buried gate, an insulation area arranged on top of the buried gate, and at least one vertical passivation layer arranged laterally between the insulation area and the at least one interface region.
However, Cheng teaches wherein the at least one trench structure (FIG. 1Q) comprises a buried gate (P.sup.+ buried gate layer 14), an insulation area (N.sup.- isolation layer 12) arranged on top of the buried gate, and at least one vertical passivation layer (N-type channel layer 24 extending vertically along sidewalls on trench, which includes trench fill material 38 and passivation step, (26)) arranged laterally between (FIG. 1H) the insulation area and the at least one interface region (field area of device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated buried-gate trench structure and insulation/passivation structure of Cheng to the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. because Cheng demonstrates such trench-gate structure as known configuration for semiconductor devices and thus would have enhanced gate reliability, protected gate metal from degradation, and enabled compact device design, thereby reducing leakage currents for improved contact formation and high-density power device support.
Regarding claim 36, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 10. Obradovic et al. does not teach wherein the at least one ohmic contact region is formed without a lithographic alignment process.
However, Cheng teaches wherein the at least one ohmic contact region (ohmic contacts 30) is formed ((20)) without a lithographic alignment process ((21), self-aligned silicide process, inherently eliminating need for additional/optional lithography step).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed ohmic contact using self-aligned silicide process taught by Cheng in modification of the formation process of Obradovic et al. in view of Bartsch et al. and Slater, JR. because self-alignment technique is known for reducing or eliminating need for additional lithographic alignment step and thus would have yielded benefit of forming contact in alignment with underlying semiconductor structure without extra lithographic alignment, thereby reducing processing steps and further supporting narrow pitch.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Shimizu (US 20140183561 A1).
Regarding claim 28, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein the at least one interface region has a thickness of below 50 nm.
However, Shimizu teaches wherein the at least one interface region (interface 225) has a thickness of below 50 nm (([0087], about 1 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided interface thickness less than 50 nm as taught by Shimizu in modification of the method of Obradovic et al. in view of Bartsch et al. and Slater, JR. because reducing thickness of interface is known technique for controlling electrical characteristics and necessitating ohmic contact formation. Shallow dopant implant at low implantation energy creates thin surface and promotes carrier segregation, thereby improving contact formation.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Yanagida et al. (“Characterization of n-type layers formed in (11–20)-4H–SiC by phosphorus ion implantation”).
Regarding claim 31, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein shallow implanting comprises implanting phosphorous at a dose of 1016/cm2.
However, Yanagida teaches wherein shallow implanting comprises implanting phosphorous (P+ ions) at a dose of 1016/cm2 (Experimental: 1.0 x 1016 cm-2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implanted phosphorous at dose of 1016/cm2 as taught by Yanagida et al. in modification of method of Obradovic et al. in view of Bartsch et al. and Slater, JR. because selection of phosphorous implantation dose is known parameter for controlling concentration of implanted n-type region and allows balance between high peak concentration production and acceptable Gaussian dopant profile spread to improve conductivity post anneal.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Obradovic et al. (US 20090057759 A1) in view of Bartsch et al. (US 20010023124 A1), Slater, JR. (US 20020179910 A1), and Konarski et al. (“Depth Profile Analysis of Phosphorus Implanted SiC Structures”).
Regarding claim 37, Obradovic et al. in view of Bartsch et al. and Slater, JR. teaches the method of claim 1. Obradovic et al. does not teach wherein after thermal treatment of the at least one interface region, an oxygen concentration peak is present at a top of the at least one interface region.
However, Konarski et al. teaches wherein after thermal treatment (thermal oxidation procedure at 1200°C after phosphorous implantation) of the at least one interface region (SiO2/SiC interface), an oxygen concentration peak (Fig. 3(a): O+ signal peaks in vicinity of P distribution, which defines oxide/SiC boundary, identifying interface region provided sample #1-4’s respective sputtering times, calculated by dividing measured thickness values by given sputtering rate) is present at a top (upper vicinity, provided greater depth/increased O sputtering time) of the at least one interface region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have performed the thermal oxidation treatment and obtain oxygen concentration profile at SiO2/SiC interface taught by Konarski et al. in modification of method of Obradovic et al. in view of Bartsch et al. and Slater, JR. because characterization of oxygen distribution (peak) at SiO2/SiC interface is known consideration in processing SiC structures and directly correlates with formation of low-resistance ohmic contacts.
Response to Arguments
Applicant's arguments filed 5/20/2026 have been fully considered but they are not persuasive.
In response to Applicant's argument that rejection to claim 1 should be withdrawn because neither Obradovic et al. nor Bartsch et al., alone or in combination, teaches or suggests "the deposited metal material forms at least one contact metal layer without chemically reacting with the wide-bandgap semiconductor material in the at least one interface region" limitation as required of claim 1 amended (as Obradovic et al. relies on formation of silicide, and Bartsch et al. relies on formation of iron carbide and nickel silicide):
Applicant’s argument is not persuasive because present rejection does not solely rely upon Obradovic et al. and/or Bartsch et al. for the limitation. Slater, JR. (US 20020179910 A1) is additionally relied upon to supply the above limitation of claim 1, as Slater, JR. teaches depositing a stable, nonreactive contact metal, e.g. platinum, on SiC substrate, which is further not interacted adversely on by the contact metal. Accordingly, Slater, JR. addresses the above limitation of claim 1 regarding contact metal layer formation without chemical reaction with semiconductor material.
Applicant further argues neither Obradovic et al. nor Bartsch et al., alone or in combination, teaches or suggests "the at least one ohmic contact region comprises more than 99% metal material" as recited by claim 1 as amended, and therefore argues that the rejection to claim 1 should be withdrawn. Applicant’s above argument is likewise not persuasive because the deposited contact metal of Slater, JR. (US 20020179910 A1) is understood under broadest reasonable interpretation to correspond to claimed ohmic contact region separate from underlying SiC interface, unless otherwise expressly disclosed. Therefore, the deposited contact metal of Slater, JR. provides the above limitation of claim 1 as claimed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have employed the deposited contact metal of Slater, JR. (US 20020179910 A1) to the ohmic contact process of Obradvoic et al. in view of Bartsch et al. and thus correspond to an ohmic contact comprising 99% metal, as best understood under broadest reasonable interpretation as separate from underlying SiC interface, unless expressly stated otherwise. Using the nonreactive contact metal of Slater, JR. in the method of Obradovic et al. in view of Bartsch et al. would prevent adverse interaction between contact metal and semiconductor material, thereby ensuring minimal interface resistance and avoiding degradation of ohmic contact performance.
Accordingly, claim 1 remains rejected.
Applicant’s argument regarding Slater et al. (US 20050104072 A1) relied upon in claim 9 is not persuasive because the present rejection now relies on:
Slater, JR. (US 20020179910 A1) for the nonreactive contact metal teaching as discussed above for limitation of claim 1 as amended, which claim 9 depends upon, in addition to the previously presented
Slater et al. (US 20050104072 A1) for backside contact and annealing limitations of claim 9.
Therefore, Applicant’s characterization of the chemical reaction occurring in Slater et al. (US 20050104072 A1) is now moot and does not overcome the rejection to claim 9.
Accordingly, Applicant’s argument to withdraw rejection to independent claim 1 (relying solely upon its alleged patentability) and its dependent claims 2-11 relied upon is not persuasive for the reasons discussed above. New claims 26-31, 33-35, and 37, dependent upon claim 1, are rejected accordingly. New claims, 32 and 36, dependent upon claim 10, which depends from claim 1, are likewise rejected for the reasons set forth above. Furthermore, limitations of claims 2-11 and 26-37 are further addressed individually by their respective prior art references with rationale for combination of references provided in the section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights