DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 11, it is stated in lines 6-7, “wherein the first serial peripheral interface couples the processor to a first memory”. Here, it is assumed the shared serial peripheral interface 216 (Figure 2) in the instant application is the claimed “first serial peripheral interface” and the memory 205 is the “first memory” (since that is the only memory that the “first serial peripheral interface 206” is used to couple the processor 102 to). However, in lines 9-10, the claim states “obtain, with the first serial peripheral interface, the updated BIOS instructions from a second memory”. But the “updated BIOS instructions” 101 are located in the equated “first memory”, not a second memory. Further, in the last two lines of the claim, it is stated “wherein the second serial peripheral interface couples the controller to the first memory and to a private memory”. Here, the private serial peripheral interface 106 is presumed to be the claimed “second serial peripheral interface”. But that private serial peripheral interface 106 does not couple the controller (i.e., controller 104) to the equated “first memory” 205. Instead, that private serial peripheral interface 106 couples the controller 104 to a different memory 216 and the private memory 204. Accordingly, the claim fails to comply with the written description requirement because it adds new matter.
All claims that are not specifically addressed are rejected due to a dependency.
Claims 6-10 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the memory" in line 18. There is insufficient antecedent basis for this limitation in the claim. More specifically, there is a “first memory”, “second memory”, and “private memory” recited earlier in the claim. Therefore, it is unclear as to which memory this limitation is referring to. The examiner will presume for examination purposes that it is referring to the “first memory”.
All claims that are not specifically addressed are rejected due to a dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jeansonne et al. (U.S. Patent Application Publication Number 2016/0055332) and Maity et al. (U.S. Patent Application Publication Number 2015/0149815).
Regarding Claim 1, Jeansonne discloses an apparatus (Figure 1, item 100) comprising:
a shared serial peripheral interface (Figure 1, item 120, paragraph 0013);
a private serial peripheral interface (Figure 1, see unnumbered connection between items 102 and 116, paragraph 0013; i.e., although the reference does not expressly state that the interface between items 102 and 116 is a serial interface, it would have been obvious to one of ordinary skill in the art to have provided a serial interface as opposed to a parallel interface, for the purpose of providing faster data transmission);
a processor (Figure 1, item 106) to transition to an on state (paragraph 0070) and execute updated basic input/output system (BIOS) instructions (Figure 1, item 110) received from the shared serial peripheral interface (paragraph 0071);
a second memory (Figure 1, item 104), wherein the shared serial peripheral interface couples the processor to the second memory (paragraph 0013);
a private memory (Figure 1, item 116, paragraph 0013); and
a controller (Figure 1, item 102, paragraph 0013) to:
obtain, with the shared serial peripheral interface, the updated BIOS instructions from the second memory (paragraphs 0016 and 0022; i.e., the system firmware 114 that is stored in private memory 116 is a duplicate of the system firmware 107 [“updated BIOS instructions”] that is stored in second memory 104, and controller 102 obtains the system firmware 107 from the second memory 104); and
copy the updated BIOS instructions to the private serial peripheral interface (paragraphs 0016 and 0022; i.e., the updated BIOS instructions 107 must be copied to the unnumbered connection between items 102 and 116 [the “private serial peripheral interface”] before reaching private memory 116),
wherein the private serial peripheral interface is inaccessible to the processor (paragraph 0013; i.e., implied given the private memory 116 is inaccessible to the processor 106), and
wherein the private serial peripheral interface couples the controller to the private memory (Figure 1, paragraph 0013).
Jeansonne does not expressly disclose a first memory;
wherein the private serial peripheral interface couples the controller to the first memory; and
wherein the controller is to copy the updated BIOS instructions to the private serial peripheral interface simultaneously with the execution of the updated BIOS instruction by the processor.
In the same field of endeavor (e.g., BIOS configuration techniques), Maity teaches a first memory (Figure 1, item 116, paragraph 0071);
wherein the private serial peripheral interface (Figure 1, item 158, paragraph 0098) couples the controller (Figure 1, item 120, paragraph 0096) to the first memory (Figure 1); and
wherein the controller is to copy the updated BIOS instructions to the private serial peripheral interface (paragraphs 0105, 0112, and 0128; i.e., the BIOS 185 [the “updated BIOS instructions”] stored within controller 120 can be “flashed” [i.e., transmitted and written] to the BIOS chip 116 over private serial peripheral interface 158) simultaneously with the execution of the updated BIOS instruction (Figure 1, item 170, paragraphs 0072 and 0104-0105; i.e., the processor 112 begins to execute the BIOS image 170; the BIOS image 170 that is currently stored in the BIOS chip 116 can be the latest version [the most “updated BIOS instructions”] – see paragraph 0074) by the processor (paragraphs 0052 and 0128; i.e., steps in the disclosed method, which include copying the updated BIOS instructions 185 to the host computer 110 [see paragraph 0128] and the processor 112 executing the BIOS instructions 170 [see paragraph 0072], can occur concurrently [simultaneously]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Maity’s teachings of BIOS configuration techniques with the teachings of Jeansonne, for the purpose of concluding the tasks of executing the BIOS and copying the updated BIOS to the private interface faster (i.e., performing the tasks concurrently as opposed to one after the other).
Regarding Claim 6, Jeansonne discloses an apparatus (Figure 1, item 100) comprising:
a first serial peripheral interface (Figure 1, item 120, paragraph 0013);
a second serial peripheral interface (Figure 1, see unnumbered connection between items 102 and 116, paragraph 0013; i.e., although the reference does not expressly state that the interface between items 102 and 116 is a serial interface, it would have been obvious to one of ordinary skill in the art to have provided a serial interface as opposed to a parallel interface, for the purpose of providing faster data transmission);
a processor (Figure 1, item 106) to transition to an on state (paragraph 0070) and execute updated basic input/output system (BIOS) instructions (Figure 1, item 110, paragraph 0071);
a second memory (Figure 1, item 104), wherein the first serial peripheral interface couples the processor to the second memory (paragraph 0013);
a private memory (Figure 1, item 116, paragraph 0013); and
a controller (Figure 1, item 102, paragraph 0013) to:
obtain, with the first serial peripheral interface, the updated BIOS instructions from the second memory (paragraphs 0016 and 0022; i.e., the system firmware 114 that is stored in private memory 116 is a duplicate of the system firmware 107 [“updated BIOS instructions”] that is stored in second memory 104, and controller 102 obtains the system firmware 107 from the second memory 104);
capture the updated BIOS instructions from the first serial peripheral interface to the second serial peripheral interface (paragraphs 0016 and 0022; i.e., the updated BIOS instructions 107 must be copied [“captured”] to the unnumbered connection between items 102 and 116 [the “private serial peripheral interface”] before reaching private memory 116),
wherein the second serial peripheral interface is inaccessible to the processor (paragraph 0013; i.e., implied given the private memory 116 is inaccessible to the processor 106), and
wherein the second serial peripheral interface couples the controller to the private memory (Figure 1, paragraph 0013).
Jeansonne does not expressly disclose a first memory;
wherein execution of the updated BIOS instructions is initiated prior to and executed simultaneously by the processor during a capture of the updated BIOS instructions;
wherein the second serial peripheral interface couples the controller to the memory (i.e., the first memory - see § 112 rejection above).
In the same field of endeavor, Maity teaches a first memory (Figure 1, item 116, paragraph 0071);
wherein execution of the updated BIOS instructions (Figure 1, item 170, paragraphs 0072 and 0104-0105; i.e., the processor 112 begins to execute the BIOS image 170; the BIOS image 170 that is currently stored in the BIOS chip 116 can be the latest version [the most “updated BIOS instructions”] – see paragraph 0074) is initiated prior to and executed simultaneously by the processor during a capture (paragraphs 0105, 0112, and 0128; i.e., the BIOS 185 [the “updated BIOS instructions”] stored within controller 120 can be “flashed”/”captured” [i.e., transmitted and written] to the BIOS chip 116 over private serial peripheral interface 158) of the updated BIOS instructions (paragraphs 0052 and 0128; i.e., steps in the disclosed method, which include copying the updated BIOS instructions 185 to the host computer 110 [see paragraph 0128] and the processor 112 executing the BIOS instructions 170 [see paragraph 0072], can occur concurrently [simultaneously]),
wherein the second serial peripheral interface (Figure 1, item 158, paragraph 0098) couples the controller (Figure 1, item 120, paragraph 0096) to the memory (Figure 1).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 6.
Regarding Claim 11, Jeansonne discloses a non-transitory machine-readable storage medium storing specific computer-executable instructions (paragraph 0087) that, when executed by a computing device (paragraph 0086), cause the computing device to at least:
transition the processor (Figure 1, item 106) to an on state (paragraph 0070);
receive, by the processor, updated basic input/out system (BIOS) instructions (Figure 1, item 110) from a first serial peripheral interface (Figure 1, item 120, paragraph 0013);
execute the updated BIOS instructions (paragraph 0071);
obtain, with the first serial peripheral interface, the updated BIOS instructions from a second memory (Figure 1, item 104, paragraphs 0016 and 0022; i.e., the system firmware 114 that is stored in private memory 116 is a duplicate of the system firmware 107 [“updated BIOS instructions”] that is stored in second memory 104, and controller 102 obtains the system firmware 107 from the second memory 104);
copy, via a controller (Figure 1, item 102, paragraph 0013), the updated BIOS instructions from the first serial peripheral interface to a second serial peripheral interface (Figure 1, see unnumbered connection between items 102 and 116, paragraph 0013; i.e., although the reference does not expressly state that the interface between items 102 and 116 is a serial interface, it would have been obvious to one of ordinary skill in the art to have provided a serial interface as opposed to a parallel interface, for the purpose of providing faster data transmission),
wherein the second serial peripheral interface is inaccessible to the processor (paragraph 0013; i.e., implied given the private memory 116 is inaccessible to the processor 106),
wherein the second serial peripheral interface couples the controller to a private memory (Figure 1, item 116, paragraph 0013).
Jeansonne does not expressly disclose wherein the first serial peripheral interface couples the processor to a first memory;
wherein a time period in which the updated BIOS instructions are copied overlaps another time period in which the updated BIOS instructions are executed by the processor, and
wherein the second serial peripheral interface couples the controller to the first memory.
In the same field of endeavor, Maity teaches wherein the first serial peripheral interface (Figure 1; i.e., there must be a connection between the CPU 112 and BIOS chip memory 116 since they communicate [paragraph 0123]; it would have been obvious to one of ordinary skill in the art to have made this a serial connection for the same reason given above) couples the processor (Figure 1, item 112) to a first memory (Figure 1, item 116, paragraph 0071);
wherein a time period in which the updated BIOS instructions are copied (paragraphs 0105, 0112, and 0128; i.e., the BIOS 185 [the “updated BIOS instructions”] stored within controller 120 can be “flashed” [i.e., transmitted and written] to the BIOS chip 116 over private serial peripheral interface 158) overlaps another time period in which the updated BIOS instructions are executed (Figure 1, item 170, paragraphs 0072 and 0104-0105; i.e., the processor 112 begins to execute the BIOS image 170; the BIOS image 170 that is currently stored in the BIOS chip 116 can be the latest version [the most “updated BIOS instructions”] – see paragraph 0074) by the processor (paragraphs 0052 and 0128; i.e., steps in the disclosed method, which include copying the updated BIOS instructions 185 to the host computer 110 [see paragraph 0128] and the processor 112 executing the BIOS instructions 170 [see paragraph 0072], can occur concurrently [simultaneously]), and
wherein the second serial peripheral interface (Figure 1, item 158, paragraph 0098) couples the controller (Figure 1, item 120, paragraph 0096) to the first memory (Figure 1).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Claims 2-5, 7-10, 12-15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeansonne and Maity as applied to claims 1, 6, and 11 above, and further in view of Anbazhagan et al. (U.S. Patent Application Publication Number 2016/0085558).
Regarding Claims 2 and 12, Jeansonne and Maity do not expressly disclose wherein the controller is to generate internal state machine variables based on a detection of the updated BIOS instructions, the controller to generate a copy of a boot block of the updated BIOS instructions and a copy of a driver execution region of the updated BIOS instructions via the internal state machine variables.
In the same field of endeavor (e.g., BIOS configuration techniques), Anbazhagan teaches wherein the controller is to generate internal state machine variables (paragraphs 0032-0035; i.e., validation of the updated boot block and DXE occurs based on a digital signature and version information [paragraphs 0038-0039]; the results of this validation is considered equivalent to the claimed “internal state machine variables”) based on a detection of the updated BIOS instructions, the controller to generate a copy of a boot block (Figure 1, item 106, paragraph 0016) of the updated BIOS instructions and a copy of a driver execution region (Figure 1, item 108, paragraph 0018) of the updated BIOS instructions via the internal state machine variables (Figure 3, items 318 and 324, paragraphs 0045-0046; i.e., updating the existing boot block and DXE with updated boot block and DXE is equivalent to the claimed “copy” step because the system copies the updated boot block and DXE to the memory 102 [Figure 1]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Anbazhagan’s teachings of BIOS configuration techniques with the teachings of Jeansonne and Maity, for the purpose of ensuring that the updated BIOS instructions are valid prior to copying them, thereby avoiding the possibility of installing a corrupt or malicious BIOS.
Regarding Claim 3, Anbazhagan teaches wherein the copy of the boot block is stored in the first memory (Figure 1, item 106), and wherein the copy of the driver execution region is stored via the private serial peripheral interface (paragraph 0009; i.e., the updated firmware including the DXE is transmitted to the memory via an interface; Huang teaches that the interface can be a private serial peripheral interface [paragraphs 0027-0028]).
Regarding Claim 4, Anbazhagan teaches wherein the copy of the boot block and the copy of the driver execution region are generated during the execution of the updated BIOS instructions (Figure 3, items 300-324, paragraphs 0045-0046; i.e., the procedure 300-324 is considered equivalent to the claimed “execution of the updated BIOS instructions”).
Regarding Claims 5 and 9, Anbazhagan teaches wherein the controller is to relocate the copy of the boot block from the memory (i.e., the memory from where the updated boot block and DXE originates) to the private memory (Figure 1, item 102) based on a signature verification operation (paragraphs 0028 and 0032).
Regarding Claim 7, Anbazhagan teaches wherein the controller is to generate a copy of a boot block (Figure 1, item 106, paragraph 0016) of the updated BIOS instructions from the first serial peripheral interface to the second memory (Figure 1, item 102, paragraph 0009; i.e., the updated firmware including the boot block is transmitted to the memory 102 via an interface; Huang teaches that the interface can be a serial peripheral interface [paragraphs 0027-0028]).
Regarding Claim 8, Anbazhagan teaches wherein the controller is to copy a driver execution region of the updated BIOS instructions from the first serial peripheral interface to the second serial peripheral interface (paragraph 0009; i.e., the updated firmware including the DXE is transmitted to the memory via two interfaces; Huang teaches that the interfaces can be serial peripheral interfaces [paragraphs 0027-0028]).
Regarding Claims 10 and 15, Maity discloses wherein the first serial peripheral interface is a shared serial peripheral interface accessible to the processor (Figure 1, item 158; i.e., the reference does not state that the processor 112 is prohibited from accessing the first serial peripheral interface 158).
Regarding Claim 13, Anbazhagan teaches wherein the copy of the boot block is stored in the first memory (Figure 1, item 106), and wherein the non-transitory machine-readable storage medium further comprises instructions to execute a signature verification operation to determine whether the copy of the boot block is corrupted (paragraphs 0028 and 0032; i.e., the purpose of a digital signature is to verify that the boot block is safe to install [e.g., not corrupted]).
Regarding Claim 14, Anbazhagan teaches instructions to relocate the copy of the boot block from the first memory (i.e., the memory from where the updated boot block and DXE originates) to the private memory (Figure 1, item 102) based on a determination that the copy of the boot block is not corrupted (paragraphs 0028 and 0032; i.e., the purpose of a digital signature is to verify that the boot block is safe to install [e.g., not corrupted]).
Regarding Claim 19, Maity discloses wherein a third serial peripheral interface couples the controller to the second memory (Figure 1, item 150, paragraph 0060; i.e., the examiner takes Official Notice that a keyboard controller style interface such as item 150 in the reference is known in the art to be a type of serial interface for peripherals [e.g., a keyboard]; for example, the AT-PS/2 keyboard interface is a serial interface; here, it can be used to couple the component/controller within host computer 110 with second memory 122).
Regarding Claim 20, Jeansonne discloses wherein the private memory is inaccessible by the processor (paragraph 0013).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses an apparatus for updating BIOS instructions.
Response to Arguments
Applicant’s arguments with respect to claims 1, 6, and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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