DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1-2, 9, and 14 are objected to because of the following informalities:
The limitation “within a range of 5 ⎕m or less” of claims 1, 9, and 14 should read “within a range of 5 µm or less.”
The limitation “via the first rein layer” of claim 2 should read “via the first resin layer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kureha (JP 6620176 B2; hereinafter Kureha) in view of Yumura (US 20050029633 A1; hereinafter Yumura).
Regarding claim 1, FIGS. 9 & 11 of Kureha teaches a semiconductor device (1 ¶ [0029]) comprising: a light emitting element (30) having a light emitting region (light emitting region of 30 ¶ [0030]); a light receiving element (20) having a light receiving region (light receiving region of 20 ¶ [0030]); and a die pad (105) made of a conductive material (e.g. lead frame ¶ [0031]), wherein the die pad (105) includes a first region (region of 105 below 20) and a second region (region of 105 below 30) having a thickness (thickness in a direction parallel to a top surface of 105) greater than that of the first region (region of 105 below 20, see Examiner annotated FIG. 11b) and surrounded by the first region (region of 105 below 20) in plan view (see FIG. 9b), wherein a through hole (201) penetrating the light receiving element (20) is provided in the light receiving element (20 ¶ [0030]), wherein the light receiving element (20) is provided on an upper surface of the first region (region of 105 below 20), wherein the light emitting element (30) is provided on an upper surface of the second region (region of 105 below 30) via a conductive first adhesive layer (e.g. silver paste, solder ¶ [0030]) inside the through hole (201), and wherein a position of an upper surface of the light emitting element (upper surface of 30) and a position of an upper surface of the light receiving element (upper surface of 20) coincide within a range of 5 μm or less (¶ [0030]). The Examiner notes the term “thickness” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as meaning the dimension of an element in the thickness direction where the thickness direction is an arbitrary direction (e.g. a direction parallel to a top surface of 10).
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Kureha does not teach wherein the light receiving element is electrically insulated from the die pad.
FIG. 1 of Yumura teaches a semiconductor device (e.g. FIG. 1) comprising: a light emitting element (11 ¶ [0021]); a light receiving element (4 ¶ [0020]); and a die pad (1, 9) made of a conductive material (¶ [0021]), wherein the light receiving element (4) is electrically insulated from the die pad (1, 9 ¶ [0020]), and wherein the light emitting element (11) and the light receiving element (4) are on the same plane (¶ [0029]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Kureha with the mount bed taught by Yumura for the purpose of providing an optocoupler with good optical coupling properties and improving manufacturing yield while insulating the light receiving element from the lead frame (¶ [0027]).
Allowable Subject Matter
Claims 9-15 are allowed.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is an examiner’s statement of reasons for allowance:
Claim 9 recites a method of manufacturing a semiconductor device comprising: (a) preparing a metal plate made of a conductive material, a light emitting element having a light emitting region, and a light receiving element having a light receiving element and provided with a through hole formed therein; (b) after the (a), selectively etching the metal plate, thereby forming a die pad including a first region and a second region having a thickness greater than that of the first region and surrounded by the first region in plan view; (c) after the (b), selectively etching the metal plate, thereby forming a plurality of lead terminals on an outer periphery of the die pad in plan view so as to be physically separated from the die pad; (d) after the (c), placing the light receiving element on an upper surface of the first region so as to be electrically insulated from the die pad; (e) after the (c), placing the light emitting element via a first adhesive layer on an upper surface of the second region so as to be located inside the through hole; and (f) after the (d) and the (e), electrically connecting the light receiving element and the plurality of lead terminals by first bonding wires and electrically connecting the light emitting element and the light receiving element by a second bonding wire, wherein a position of an upper surface of the light emitting element and a position of an upper surface of the light receiving element coincide within a range of 5 µm or less.
FIGS. 10-11 of Kureha teach a method of manufacturing a semiconductor device comprising: (a) preparing a metal plate made of a conductive material, a light emitting element having a light emitting region, and a light receiving element having a light receiving element and provided with a through hole formed therein; (b) after the (a), forming a die pad including a first region and a second region having a thickness greater than that of the first region and surrounded by the first region in plan view; (c) after the (b), selectively etching the metal plate, thereby forming a plurality of lead terminals on an outer periphery of the die pad in plan view so as to be physically separated from the die pad; (d) after the (c), placing the light receiving element on an upper surface of the first region so as to be electrically insulated from the die pad; (e) after the (c), placing the light emitting element via a first adhesive layer on an upper surface of the second region so as to be located inside the through hole; and (f) after the (d) and the (e), electrically connecting the light receiving element and the plurality of lead terminals by first bonding wires and electrically connecting the light emitting element and the light receiving element by a second bonding wire, wherein a position of an upper surface of the light emitting element and a position of an upper surface of the light receiving element coincide within a range of 5 µm or less.
However, the prior art does not teach or reasonably suggest “selectively etching the metal plate, thereby forming the die pad including the first region and the second region having the thickness greater than that of the first region and surrounded by the first region in the plan view” together with all the limitations of claim 9 as claimed. Claims 10-13 are allowable insofar as they depend on and require all the limitations of claim 9.
Claim 14 recites a method of manufacturing a semiconductor device comprising: (a) preparing a first metal plate made of a conductive material, a second metal plate made of a conductive material, a light emitting element having a light emitting region, and a light receiving element having a light receiving region and provided with a through hole provided therein;(b) after the (a), selectively etching the first metal plate, thereby forming a die pad including a first region and a second region having a thickness greater than that of the first region and surrounded by the first region in plan view and forming a plurality of first lead terminal members on an outer periphery of the die pad in plan view so as to be physically separated from the die pad; (c) after the (a), selectively etching the second metal plate, thereby forming a plurality of second lead terminal members; (d) after the (b) and the (c), mounting an upper surface of the light emitting element, an upper surface of the light receiving element, and upper surfaces of the plurality of second lead terminal members on a base material such that the light emitting element is located inside the through hole; (e) after the (d), attaching an upper surface of the second region to a lower surface of the light emitting element via a conductive first adhesive layer and attaching upper surfaces of the plurality of first lead terminal members to lower surfaces of the plurality of second lead terminal members via conductive third adhesive layers, respectively, such that the light receiving element and the first region are physically separated; (f) after the (e), providing a resin layer between the light receiving element and the die pad, the light emitting element, the first adhesive layer, the plurality of first lead terminal members, and the plurality of second lead terminal members so as to fill the through hole; (g) after the (f), removing the base material; and (h) after the (g), electrically connecting the light receiving element and the plurality of second lead terminal members by first bonding wires and electrically connecting the light emitting element and the light receiving element by a second bonding wire, wherein a position of the upper surface of the light emitting element and a position of the upper surface of the light receiving element coincide within a range of 5 µm or less.
FIGS. 10-11 of Kureha teach a method of manufacturing a semiconductor device comprising: (a) preparing a metal plate made of a conductive material, a light emitting element having a light emitting region, and a light receiving element having a light receiving element and provided with a through hole formed therein; (b) after the (a), forming a die pad including a first region and a second region having a thickness greater than that of the first region and surrounded by the first region in plan view; (c) after the (b), selectively etching the metal plate, thereby forming a plurality of lead terminals on an outer periphery of the die pad in plan view so as to be physically separated from the die pad; (d) after the (c), placing the light receiving element on an upper surface of the first region so as to be electrically insulated from the die pad; (e) after the (c), placing the light emitting element via a first adhesive layer on an upper surface of the second region so as to be located inside the through hole; and (f) after the (d) and the (e), electrically connecting the light receiving element and the plurality of lead terminals by first bonding wires and electrically connecting the light emitting element and the light receiving element by a second bonding wire, wherein a position of an upper surface of the light emitting element and a position of an upper surface of the light receiving element coincide within a range of 5 µm or less.
However, the prior art fails to teach or reasonably suggest “preparing a first metal plate made of a conductive material, a second metal plate made of a conductive material… selectively etching the first metal plate, thereby forming a die pad including a first region and a second region having a thickness greater than that of the first region” together with all the limitations of claim 14 as claimed. Claim 15 is allowable insofar as it depends on and requires all the limitations of claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the semiconductor device according to claim 1, further comprising a first resin layer provided on the upper surface of the first region such that an upper surface of the first resin layer is flush with the upper surface of the second region, wherein the light receiving element is provided on the upper surface of the first region via the first resin layer.
Kureha as modified teaches the semiconductor device according to claim 1.
However, the prior art fails to teach or reasonably suggest “a first resin layer provided on the upper surface of the first region such that an upper surface of the first resin layer is flush with the upper surface of the second region, wherein the light receiving element is provided on the upper surface of the first region via the first resin layer” together with all the limitations of claims 1 and 2 as claimed. Claim 3 contains allowable subject matter insofar as it depends on and requires all the limitations of claims 1 and 2.
Claim 4 recites the semiconductor device according to claim 1, further comprising an insulating second adhesive layer provided on the upper surface of the first region, wherein the light receiving element is provided on the upper surface of the first region via the second adhesive layer, and wherein a height from a position of the upper surface of the first region to a position of the upper surface of the second region is in a range of 50% or more and 70% or less of the thickness of the second region.
Kureha as modified teaches the semiconductor device according to claim 1.
However, the prior art fails to teach or reasonably suggest “an insulating second adhesive layer provided on the upper surface of the first region, wherein the light receiving element is provided on the upper surface of the first region via the second adhesive layer, and wherein a height from a position of the upper surface of the first region to a position of the upper surface of the second region is in a range of 50% or more and 70% or less of the thickness of the second region” together with all the limitations of claims 1 and 4 as claimed. Claim 5 contains allowable subject matter insofar as it depends on and requires all the limitations of claims 1 and 4.
Claim 6 recites the semiconductor device according to claim 1, further comprising: a plurality of lead terminals provided on an outer periphery of the die pad in plan view so as to be physically separated from the die pad, and made of a conductive material; and bonding wires electrically connecting the light receiving element and the plurality of lead terminals, wherein a position of an upper surface of each of the plurality of lead terminals is higher than a position of the upper surface of the second region, and wherein a second resin layer is provided between the light receiving element and the die pad, the light emitting element, the first adhesive layer, and the plurality of lead terminals so as to fill the through hole.
Kureha as modified teaches the semiconductor device according to claim 1, and FIGS. 9 & 11 of Kureha further teaches further comprising: a plurality of lead terminals (101) provided on an outer periphery of the die pad (105) in plan view so as to be physically separated from the die pad (105), and made of a conductive material (¶ [0031]); and bonding wires (21) electrically connecting the light receiving element (20) and the plurality of lead terminals (101).
FIG. 8 of Kureha further teaches wherein a second resin layer (41) is provided between the light receiving element (20) and the die pad (102b ¶ [0026]), the light emitting element (30), and the plurality of lead terminals (101) so as to fill the through hole (201 ¶ [0027]).
However, the prior art fails to teach or reasonably suggest “wherein a position of an upper surface of each of the plurality of lead terminals is higher than a position of the upper surface of the second region” together with all the limitations of claims 1 and 6 as claimed. Claims 7-8 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 1 and 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891