DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 20 is objected to because of the following informalities:
The limitation “electrical passivate” of claim 20 should read “electrically passivate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22, 27-28, 30-32, and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US 20140264888 A1; hereinafter Hsu).
Regarding claim 21, FIGS. 3A-E of Hsu teach a method for manufacturing a semiconductor die, the method comprising: providing the semiconductor die (die shown in FIG. 3A) including a base body (10) comprising a semiconductor material (¶ [0037]) and a surface with two contact areas (surface of 10 contacting 10A-10B) having contact pads (10A-10B) at which the semiconductor die (die shown in FIG. 3A) is electrically contactable (¶ [0038]); applying a passivation layer (20) for electrical passivation (¶ [0041],[0043]) to the surface of the semiconductor die (surface of 10 contacting 10A-10B) thereby providing areas free of passivation (exposed areas of 10A-10B) allowing external access to each contact pad (10A-10B); and metallizing parts of the surface of the semiconductor die (die shown in FIG. 3B) with metal caps (31-32), the metal caps (31-32) directly contacting the contact pads (10A-10B ¶ [0045]).
Regarding claim 22, Hsu teaches the method according to claim 21, and FIGS. 3A-E of Hsu teach wherein the method is performed in the recited order (see FIG. 1).
Regarding claim 27, Hsu teaches the method according to claim 21, and FIG. 3E of Hsu further teaches wherein the surface with the two contact areas (surface of 10 contacting 10A-10B) is a frontside surface (101 ¶ [0039]), wherein a first contact area of the two contact areas (area of 10 below 10A) is arranged near a first side of the semiconductor die (left side of die shown in FIG. 3E) and a second contact area of the two contact areas (area of 10 below 10B) is arranged near a second side of the semiconductor die (right side of die shown in FIG. 3E), the second side (right side) being arranged opposite to the first side (left side), wherein the first side (left side) and the second side (right side) are perpendicular to the frontside surface (101), and wherein the metal caps (31-32) are contiguously applied to the first side (left side) and the second side (right side) and respectively to each four sides adjacent to the first or second side of the semiconductor die (sides adjacent to left and right sides including 100-101, see FIGS. 2I & 3E).
Regarding claim 28, Hsu teaches the method according to claim 21, and FIG. 4 of Hsu further teaches further comprising externally contacting the semiconductor die (contacting die shown in FIG. 3E via solder S) via the metal caps (31-32 ¶ [0050]).
Regarding claim 30, the method according to claim 21, and FIG. 3E of Hsu further teaches wherein the metal caps (31-32) are directly applied to the passivation layer (20).
Regarding claim 31, Hsu teaches the method according to claim 21, and Hsu further teaches wherein the metal caps (e.g. 310, 320) are applied by a dipping process (¶ [0046] “dipping silver”).
Regarding claim 32, Hsu teaches the method according to claim 21, wherein the metal caps (31-32) comprise two or three different stacked layers (e.g. 310-312, 320-322) applied by two or three metalizing steps (e.g. dipping silver, electroplating ¶ [0046]).
Regarding claim 36, Hsu teaches the method according to claim 21, and FIGS. 1-2F of Hsu teach wherein several semiconductor dies (e.g. semiconductor dies shown in FIG. 2E) are manufactured in parallel by a wafer level chip scale package process (¶ [0037]-[0042]).
Claims 16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Theuss (US 20070273046 A1; hereinafter Theuss).
Regarding claim 16, FIG. 27 of Theuss teaches a semiconductor die (1) comprising: a base body (7) comprising: a semiconductor material (¶ [0078]); and a surface with two contact areas (15 ¶ [0075]) having contact pads (6) at which the semiconductor die (1) is electrically contactable and two metal caps (14) arranged directly at the contact pads (¶ [0077]).
Regarding claim 20, Theuss teaches the semiconductor die according to claim 16, and FIG. 27 of Theuss further teaches further comprising a passivation layer (11) configured to electrical passivate the surface of the semiconductor die (surface of 7), wherein areas free of passivation layer are provided allowing for external access to each contact pad (6 ¶ [0081]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Theuss in view of Hsu.
Regarding claim 16, FIG. 27 of Theuss teaches a semiconductor die (1 ¶ [0082]) comprising: a base body (7) comprising: a semiconductor material (¶ [0078]); and a surface with two contact areas (15 ¶ [0075]) having contact pads (14) at which the semiconductor die (1) is electrically contactable (¶ [0077]).
Theuss does not teach two metal caps arranged directly at the contact pads.
FIG. 3E of Hsu teaches a semiconductor die (e.g. FIG. 3E) comprising: a base body (10) comprising: a semiconductor material (¶ [0037]); and a surface with two contact areas (areas of 10 contacting 10A-10B) having contact pads (10A-10B) at which the semiconductor die (10) is electrically contactable (¶ [0038]) and two metal caps (31-32) arranged directly at the contact pads (10A-10B ¶ [0045]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor die taught by Theuss with the metal caps taught by Hsu for the purpose of increasing the contact area and bonding strength of the electronic package structure.
Regarding claim 17, Theuss as modified teaches the semiconductor die according to claim 16, and FIG. 27 of Theuss further teaches further comprising two interlayers (6) connecting the contact areas (15) with the contact pads (14 ¶ [0076]-[0077]).
Regarding claim 18, Theuss as modified teaches the semiconductor die according to claim 16, and FIGS. 1 & 27 of Theuss further teaches wherein the surface with the two contact areas (15) is a frontside surface (16 ¶ [0075] “top side”), wherein a first contact area of the two contact areas (first instance of 15) is arranged near a first side of the die (left side of 1 shown in FIG. 27) and a second contact area of the two contact areas (second instance of 15) is arranged near a second side of the die (right side of 1 shown in FIG. 27), the second side (right side of 1) being arranged opposite to the first side (left side of 1), wherein the first side (left side of 1) and the second side (right side of 1) are perpendicular to the frontside surface (16).
FIGS. 2I & 3E of Hsu further teaches wherein the metal caps (31-32) are contiguously arranged at a first side (left side of the structure shown in FIG. 3E) and a second side (right side of the structure shown in FIG. 3E) and respectively to each four sides adjacent to the first or second side of the semiconductor die (see FIGS. 2I and 3E).
Regarding claim 19, Theuss as modified teaches the semiconductor die according to claim 16, and FIG. 27 of Theuss further teaches wherein the contact areas (15) are structural elements comprising conductive metals (¶ [0048],[0060]).
Regarding claim 20, Theuss as modified teaches the semiconductor die according to claim 16, and FIG. 27 of Theuss further teaches further comprising a passivation layer (11) configured to electrically passivate the surface of the semiconductor die (¶ [0081],[0106]), wherein areas free of passivation layer (11) are provided allowing for external access to each contact pad (15, see FIG. 27).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Harakawa et al. (US 4805074 A; hereinafter Harakawa).
Regarding claim 26, Hsu teaches the method according to claim 21, FIG. 3C of Hsu teaches forming a metal cap (first instance of 320) on a second side of the semiconductor die (right side of die shown in FIG. 3C) by dipping silver in a first metallizing (¶ [0046]); and forming a metal cap (second instance of 320) on a first side of the semiconductor die (left side of die shown in FIG. 3C) by dipping silver in a first metallizing (¶ [0046]).
Hsu does not teach further comprising: hardening a metal cap on a second side of the semiconductor die after first metallizing; and hardening a metal cap on a first side of the semiconductor die after second metallizing.
Harakawa teaches a method of forming an electronic device (e.g. FIG. 1) including dipping the electronic device into a silver paste solution and hardening to form a metal cap (10, col. 6 lines 50-58).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing a semiconductor die taught by Hsu with the hardening of the silver paste taught by Harakawa for the purpose of forming hardened metal caps on the semiconductor die.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Byun et al. (US 20180182558 A1; hereinafter Byun).
Regarding claim 29, Hsu teaches the method according to claim 21, further comprising externally contacting the semiconductor die (contacting die shown in FIG. 3E) via soldering (S) the metal caps (31-32) to a substrate body (40 ¶ [0050]).
Hsu does not teach externally contacting the semiconductor die via soldering the metal caps to a printed circuit board.
FIG. 5 of Byun teaches a semiconductor die comprising metal caps (131-132) externally contacting a printed circuit board (210 ¶ [0134]) via soldering (231-232 ¶ [0136]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the semiconductor die taught by Hsu with the die contacting the PCB taught by Byun for the purpose of providing protection from electrostatic discharge (¶ [0005] of Hsu,¶ [0087] of Byun) to the PCB.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Chinnusamy (US 20170032981 A1; hereinafter Chinnusamy).
Regarding claim 33, Hsu teaches the method according to claim 21, wherein the metal caps (31-32) comprise metals or a mixture of metals (e.g. Ag, Ni, Sn ¶ [0046]).
Hsu does not teach wherein the metal caps comprise metals or a mixture of metals which is different from that of the contact pads.
FIG. 1b of Chinnusamy teaches a series of semiconductor dies comprising contact pads (112), wherein the contact pads include a metal material (e.g. aluminum, copper, palladium ¶ [0022]).
Thus, Hsu in view of Chinnusamy teaches wherein the metal caps (31-32 of Hsu) comprise metals or a mixture of metals (e.g. Ag, Ni, Sn) which is different from that of the contact pads (10A-10B of Hsu/114 of Chinnusamy, e.g. aluminum, copper, palladium).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method for manufacturing the semiconductor die taught by Hsu with the material of the contact pads taught by Chinnusamy since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Vermang et al. (US 20120192943 A1; hereinafter Vermang).
Regarding claim 34, Hsu teaches the method according to claim 21.
Hsu does not teach wherein the passivation layer is applied by an atomic layer deposition process.
FIGS. 9-10 of Vermang teach forming a passivation layer (3) on a silicon substrate (2); wherein the passivation layer (3) is applied by an atomic layer deposition process (¶ [0069]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the semiconductor die taught by Hsu with the ALD process taught by Vermang for the purpose of providing excellent passivation at low deposition temperatures (¶ [0051]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Vermang, and further in view of Kot et al. (M. Kot, C. Das, Z. Wang, K. Henkel, Z. Rouissi, K. Wojciechowski, H. J. Snaith, D. Schmeisser, ChemSusChem 2016, 9, 3401.).
Regarding claim 35, Hsu as modified teaches the method according to claim 34.
Hsu as modified does not teach wherein the atomic layer deposition process is performed at a temperature lower than 80 °C.
Kot teaches an atomic layer deposition process (“Al2O3 layer grown at room temperature by atomic layer deposition”) performed at room temperature (pg. 3405 paragraph 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the semiconductor die taught by Hsu with the room temperature ALD process taught by Kot for the purpose of forming the passivation layer with excellent passivation without the risk of degrading underlying components.
Allowable Subject Matter
Claims 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 23 recites the method according to claim 21, further comprising: loading the semiconductor die on a first side to a first metallization tape; metallizing a contiguous area of the semiconductor die not covered by the first metallization tape including at least one contact pad; loading the semiconductor die on a second side to a second metallization tape; and metallizing a contiguous area of the semiconductor die not covered by the second metallization tape including at least one contact pad.
Hsu teaches the method according to claim 21.
However, the prior art fails to teach or reasonably suggest “loading the semiconductor die on a first side to a first metallization tape; metallizing a contiguous area of the semiconductor die not covered by the first metallization tape including at least one contact pad; loading the semiconductor die on a second side to a second metallization tape; and metallizing a contiguous area of the semiconductor die not covered by the second metallization tape including at least one contact pad” together with all the limitations of claims 21 and 23 as claimed. Claims 24-25 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 21 and 23.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891