DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 is objected to because of the following informalities:
Claim 18 is not clear because it recites, in line 3, the limitation “wherein the display module comprising a data drive circuit and a display panel”. For the purpose of examination, the Examiner assumes the above limitation of “wherein the display module comprising a data drive circuit and a display panel” (as recited in line 3) is:
“wherein the display module comprising a data drive circuit and a display panel” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 16-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KIM et al. (U.S 2023/0071490 A1).
As to claim 1, KIM et al. disclose in Fig. 4B a display panel (Fig. 4B), comprising: a base substrate (110), comprising a first display region (CPA) and a second display region (CAA) at least partially surrounding the first display region (CPA); a drive circuit layer (“circuit layer” 120 including “first and second driving transistors” TRP1 and TRP2 constituting the scan driving circuit SDC, para. [0149]) on a side of the base substrate (110) (Fig. 4B, para. [0118], [0149]), wherein the drive circuit layer (“circuit layer” 120) comprises a plurality of first pixel circuits (“pixel transistors” TR1) and a plurality of second pixel circuits (“pixel transistors” TR2) that are disposed in the second display region (CAA) (Fig. 4B, para. [0120], [0148]-[0149]); and a first electrode layer (AE1), at least comprising a plurality of first-type electrode patterns (CN2, V1-V3), wherein the plurality of first-type electrode patterns (CN2, V1-V3) comprise a plurality of first electrode patterns (see all patterns in CPA) in the first display region (CPA) and a plurality of second electrode patterns (CN1, CN0) in the second display region (CAA) (Fig. 4B); wherein at least two of the plurality of first electrode patterns (see all patterns in CPA) are connected to one of the plurality of first pixel circuits (“pixel transistors” TR1), and at least two of the plurality of second electrode patterns (CN1, CN0) are connected to one of the plurality of second pixel circuits (“pixel transistors” TR2) (see Fig. 4B).
As to claim 2, as applied to claim 1 above, KIM et al. disclose in Fig. 4B all claimed limitations including the display panel further comprising: a plurality of first connection traces (see first traces in layer 120) in the first display region (CPA) (Fig. 4B); a plurality of second connection traces (CE) extending from the second display region (CAA) to the first display region (CPA) along a pixel row direction (Fig. 4B, para. [0151]); a plurality of third connection traces (see third traces in layer 120) in the second display region (CAA) (Fig. 4B); wherein at least two of the plurality of first electrode patterns (CN2, V1-V3) are connected via one of the plurality of first connection traces (Fig. 4B), one of the at least two of the plurality of first electrode patterns (CN2, V1-V3) is connected to one of the plurality of first pixel circuits (TR1) via one of the plurality of second connection traces (see second traces in layer 120) (Fig. 4B), at least two of the plurality of second electrode patterns (CN1, CN0) are connected via one of the plurality of third connection traces (see third traces in layer 120) (Fig. 4B), and one of the at least two of the plurality of second electrode patterns (CN2, V1-V3) is connected to one of the plurality of second pixel circuits (TR2) (Fig. 4B).
As to claim 16, as applied to claims 1 and 2 above, KIM et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein the plurality of third connection traces (see third traces in layer 120) and the first electrode layer (AE1) are disposed in a same layer (Fig. 4B), and the plurality of first connection traces (see first traces in layer 120) and the plurality of second connection traces (see second traces in layer 120) are disposed between the drive circuit layer (120) and the first electrode layer (AE1) (Fig. 4B).
As to claim 17, KIM et al. disclose in Fig. 4B a display panel (Fig. 4B a display module, comprising: a data drive circuit (“first and second driving transistors” TRP1 and TRP2, para. [0149]) and ta display panel (Fig. 4B), wherein the display panel (Fig. 4B) includes: a base substrate (110), comprising a first display region (CPA) and a second display region (CAA) at least partially surrounding the first display region; a drive circuit layer (“circuit layer” 120 including “first and second driving transistors” TRP1 and TRP2 constituting the scan driving circuit SDC, para. [0149]) on a side of the base substrate (110) (Fig. 4B, para. [0118], [0149]), wherein the drive circuit layer (“circuit layer” 120) comprises a plurality of first pixel circuits (“pixel transistors” TR1) and a plurality of second pixel circuits (“pixel transistors” TR2) that are disposed in the second display region (CAA) (Fig. 4B, para. [0120], [0148]-[0149]); and a first electrode layer (AE1), at least comprising a plurality of first-type electrode patterns (CN2, V1-V3), wherein the plurality of first-type electrode patterns (CN2, V1-V3)) comprise a plurality of first electrode patterns (see all patterns in CPA) in the first display region (CPA) and a plurality of second electrode patterns (CN1, CN0) in the second display region (CAA) (Fig. 4B); wherein at least two of the plurality of first electrode patterns (see all patterns in CPA) are connected to one of the plurality of first pixel circuits (“pixel transistors” TR1), and at least two of the plurality of second electrode patterns (CN1, CN0) are connected to one of the plurality of second pixel circuits (“pixel transistors” TR2) (see Fig. 4B); and the data drive circuit (TRP1, TRP2) is connected to first data lines (DL1), third data lines (DL1-DMm include third data lines, para. [0060]), fourth data lines (DL1-DMm include fourth data lines, para. [0060), and seventh data lines (DL1-DMm include seventh data lines, para. [0060) that are in the display panel (Fig. 4B).
As to claim 18, KIM et al. disclose in Fig. 4B a display device, comprising: a display module (Fig. 4B) and an optical sensor (200), wherein the display module (Fig. 4B) comprising a data drive circuit (“first and second driving transistors” TRP1 and TRP2, para. [0149]) and a display panel (Fig. 4B); wherein the display panel (Fig. 4B) includes: a base substrate (110), comprising a first display region (CPA) and a second display region (CAA) at least partially surrounding the first display region; a drive circuit layer (“circuit layer” 120 including “first and second driving transistors” TRP1 and TRP2 constituting the scan driving circuit SDC, para. [0149]) on a side of the base substrate (110) (Fig. 4B, para. [0118], [0149]), wherein the drive circuit layer (“circuit layer” 120) comprises a plurality of first pixel circuits (“pixel transistors” TR1) and a plurality of second pixel circuits (“pixel transistors” TR2) that are disposed in the second display region (CAA) (Fig. 4B, para. [0120], [0148]-[0149]); and a first electrode layer (AE1), at least comprising a plurality of first-type electrode patterns (CN2, V1-V3), wherein the plurality of first-type electrode patterns (CN2, V1-V3) comprise a plurality of first electrode patterns (see all patterns in CPA) in the first display region (CPA) and a plurality of second electrode patterns (CN1, CN0) in the second display region (CAA) (Fig. 4B); wherein at least two of the plurality of first electrode patterns (see all patterns in CPA) are connected to one of the plurality of first pixel circuits (“pixel transistors” TR1), and at least two of the plurality of second electrode patterns (CN1, CN0) are connected to one of the plurality of second pixel circuits (“pixel transistors” TR2) (see Fig. 4B); and an orthogonal projection of the optical sensor (200) on the display panel (100-1, Fig. 5) is at least partially overlapped with the first display region (CPA) in the display panel (100-1) (Figs. 4B-5, para. [0200]).
As to claim 19, as applied to claim 17 above above, KIM et al. disclose in Fig. 4B all claimed limitations including the limitation: wherein the display panel (Fig. 4B) further comprises: a plurality of first connection traces (see first traces in layer 120) in the first display region (CPA) (Fig. 4B); a plurality of second connection traces (CE) extending from the second display region (CAA) to the first display region (CPA) along a pixel row direction (Fig. 4B); a plurality of third connection traces (see third traces in layer 120) in the second display region (CAA); wherein at least two of the plurality of first electrode patterns (CN2, V1-V3) are connected via one of the plurality of first connection traces (see first traces in layer 120), one of the at least two of the plurality of first electrode patterns (CN2, V1-V3) is connected to one of the plurality of first pixel circuits (TR1) via one of the plurality of second connection traces (see second traces in layer 120), at least two of the plurality of second electrode patterns (CN1, CN0) are connected via one of the plurality of third connection traces (see third traces in layer 120), and one of the at least two of the plurality of second electrode patterns (CN1, CN0) is connected to one of the plurality of second pixel circuits (“pixel transistors” TR2) (Fig. 4B).
Allowable Subject Matter
Claims 3-15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 April 4, 2026
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