DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 11, and 12 have been amended.
Claims 3-9 have been cancelled.
Claims 16-22 have been added.
Claims 1, 2, and 10-22 have been examined.
The specification, drawing, and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10-13, 15, 16, 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2019/0243700 by Brewer (as cited by Applicant and hereinafter referred to as “Brewer”) in view of US Publication No.2021/0200667 by Bernstein et al. (hereinafter referred to as “Bernstein”).
Regarding claims 1 and 12, taking claim 1 as representative, Brewer discloses:
a system comprising: …a plurality of memory nodes implemented by chiplets …(Brewer discloses, at Figure 1B and related description, a system having plurality of chiplets. The chiplets include EP circuitry that can be, as disclosed at ¶ [0056], memory.); and
a network fabric connected to each of the plurality of memory nodes (Brewer discloses, at Figure 1B and related description, the chiplets are implemented on an interposer, which discloses a network fabric connected to each of the memory nodes.).
Brewer does not explicitly disclose a memory pool that is configured to provide shared access to a memory capacity to external processors, the memory pool including and the aforementioned chiplets collectively comprise the memory capacity
However, in the same field of endeavor (e.g., memory) Bernstein discloses:
a memory pool that provides shared access to external processors to collected memory resources (Bernstein discloses, at Figure 16 and related description, a memory pool providing memory access to processors, which discloses a memory pool that is configured to provide shared access to a memory capacity to external processors, the memory pool including and collective memory capacity.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include the use of memory pools disclosed by Bernstein in order to improve performance by improving utilization and allocation of memory resources. See, e.g., Bernstein, ¶ [0030].
Regarding claim 2, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
a plurality of interface blocks …that provide a common interface to the network fabric to …processors (Brewer discloses, at Figure 1B and related description, CPI (common protocol interface) circuits, which discloses providing a common interface to processors, e.g., processor 110 shown in Figure 2.).
Brewer does not explicitly disclose that the aforementioned interface blocks are implemented as chiplets and that the aforementioned processors are external processors.
However, Brewer discloses interface chiplets, e.g., at ¶ [0058], and providing data to external devices, e.g., at ¶ [0123]. It would have been obvious to a person having ordinary skill in the art at the time of invention to modify Brewer to implement the CPI circuitry as chiplets and provide data to external processors because doing so improves flexibility, configurability, and utility.
Regarding claim 10, Brewer discloses the elements of claim 2, as discussed above. Brewer also discloses:
the common interface comprises one or more of DDRx, LPDDRx, GDDRx, PCIe, UCIe and CXL (Brewer discloses, at ¶ [0058], the CPI utilizes PCIe.).
Regarding claim 11, Brewer discloses the elements of claim 2, as discussed above. Brewer also discloses:
the memory nodes connect to the network fabric via the plurality of interface blocks (Brewer discloses, at Figure 1B and related description, the chiplets are implemented on an interposer, which discloses a network fabric connected to each of the memory nodes via the CPI circuitry, i.e., interface blocks.).
Regarding claims 13 and 16, taking claim 16 as representative, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
the network fabric implements a mesh topology for connecting the plurality of memory nodes (Brewer discloses, at ¶ [0088], implementing a mesh fabric.).
Regarding claim 15, Brewer discloses the elements of claim 12, as discussed above. Brewer also discloses:
the memory type of the memory nodes comprises one or more of SRAM, DRAM, MRAM, and Flash (Brewer discloses, at Figure 1B and related description, memory chiplets, which discloses each memory chiplet having a memory type. As disclosed at ¶ [0118, the memory can include DRAM.).
Regarding claim 18, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
the network fabric comprises a silicon substrate or non-silicon substrate (Brewer discloses, at ¶ [0005], silicon and organic interposers.).
Regarding claim 19, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
one of the plurality of memory nodes implements a first memory type, and a second one of the plurality of memory nodes implements a second memory type…(Brewer discloses, at Figure 1B and related description, memory chiplets, which discloses each memory chiplet having a memory type.).
Brewer does not explicitly discloses the first and second memory types being different. However, Brewer discloses different memory types, e.g., at ¶ [0118]. It would have been obvious to a person having ordinary skill in the art at the time of invention to modify Brewer to utilize different memory types because doing so improves flexibility, configurability, and utility.
Regarding claim 20, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
one of the plurality of memory nodes includes a memory controller, and a second one of the plurality of memory nodes does not include a memory controller (Brewer discloses, at Figure 1B, Figure 2, and related description, nodes that include memory controllers and nodes that do not include memory controllers.).
Regarding claim 21, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
one of the plurality of memory nodes includes a network router, and a second one of the plurality of memory nodes does not include a network router (Brewer discloses, at Figure 1A, Figure 1B, and related description, nodes that include communication networks, i.e., a network router, and nodes that do not include communication networks.).
Regarding claim 22, Brewer discloses the elements of claim 1, as discussed above. Brewer also discloses:
one or more compute chips connected to the network fabric (Brewer discloses, at Figure 1B and related description, a system having plurality of chiplets. The chiplets include EP circuitry that can be, as disclosed at ¶ [0056], a processor, i.e. a compute chip.).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brewer in view of US Publication No. 2020/0393991 by Kachare et al. (hereinafter referred to as “Kachare”).
Regarding claims 14 and 17, taking claim 17 as representative, Brewer discloses the elements of claim 1, as discussed above. Brewer does not explicitly disclose the network fabric implements a folded torus topology for connecting the plurality of memory nodes.
However, in the same field of endeavor (e.g., data movement) Kachare discloses:
folded torus topology (Kachare discloses, at ¶ [0042], a folded torus topology.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer’s topology to utilize a folded torus, as disclosed by Kachare because this is known to be a high-performance implementation. See Kachare, ¶ [0042].
Response to Arguments
On page 6 of the response filed June 27, 2025 (“response”), the Applicant argues that the objections to the drawings, specification, and claims are overcome.
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Accordingly, the objections are withdrawn.
On page 7 of the response the Applicant argues the § 112 rejections should be withdrawn.
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Accordingly, the rejections are withdrawn.
On page 7 of the response the Applicant argues, “there is no explicit or inherent disclosure in Brewer of a memory pool as is now even more explicitly set forth in the claims. Rather, Brewer only discloses that a plurality of chiplets can be arranged on an interposer, and that a chiplet can contain a memory and a memory controller. This would not necessarily provide a memory pool as claimed.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. As indicated above, Bernstein disclose providing a memory pool for shared access to external processors. See, e.g., Bernstein’s Figure 16 and related description. The advantages of using memory pools are well-known, as indicated above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183