Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 27, 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (hereinafter Hu, US 2016/0372070) in view of Du. et al (hereinafter Du, US 2023/0060545).
In regards to independent claim 1, Hu teaches a display substrate, comprising a first node control circuit (Hu, Shift Register for Node PU, Fig. 2 [0033]), and the first node control circuit is configured to control a potential of a first node (Hu, Fig. 2, input to pull up node PU);
the first node control circuit includes a first transistor and a second transistor (Hu, Fig. 2, Item T3, T4);
a gate electrode of the first transistor is electrically connected to a first control terminal (Hu, Fig. 2, Item T3 connected to ck4);,
a first electrode of the first transistor is electrically connected to a first voltage terminal (Hu, Fig. 2, Item T3 connected to Out_n-1)), and
a second electrode of the first transistor is electrically connected to the first node (Hu, Fig. 2, Item T3 connected to PU);
a gate electrode of the second transistor is electrically connected to a second control terminal (Hu, Fig. 2, Item T4 connected to ck2),
a first electrode of the second transistor is electrically connected to the first node (Hu, Fig. 2, Item T4 connected to PU), and
a second electrode of the second transistor is electrically connected to a second voltage terminal (Hu, Fig. 2, Item T4 connected to OUT_N+1);
the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure (Hu, Fig. 2, first transistor connected to ck4 and OUT_N-1, second transistor connected to ck2 and OUT_N+1, Examiner Note: Clarification of connection structure is suggested as any connections between disparate elements can be interpreted9 as part of a connection structure).
Hu fails to explicitly teach:
a driving circuit arranged on a base substrate,
the display substrate further includes a first connection structure and a second connection structure arranged on the base substrate;
the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.
Du teaches :
a driving circuit arranged on a base substrate (Du, Fig. 2, 13 and 14 on substrate 1),
the display substrate further includes a first connection structure and a second connection structure arranged on the base substrate (Du, Fig. 5B, ie Input lines EML, GL, RCL on substrate 1);
It would have been obvious to one of ordinary skill in the art, having the teachings of Hu and Du before him before the effective filing date of the claimed invention, to modify the shift register taught by Hu to include the manufacturing method of Du in order to obtain a shift register formed on a base substrate with multiple interconnected layers. One would have been motivated to make such a combination because it reduces the are required for the circuit by using known methods of multilayer circuit fabrication.
In regards to dependent claim 27, Hu teaches a method for manufacturing the display substrate according to claim 1, comprising:
forming the first transistor, the second transistor, (Hu, Fig. 2, Item T3, T4) the first connection structure, and the second connection structure (Hu, Fig. 2, first transistor connected to ck4 and OUT_N-1, second transistor connected to ck2 and OUT_N+1, Examiner Note: Clarification of connection structure is suggested as any connections between disparate elements can be interpreted9 as part of a connection structure);
arranging the first transistor and the first connection structure to be electrically connected to each other; and/or, arranging the second transistor and the second connection structure to be electrically connected to each other (Hu, Fig. 2, Item T3, T4 both connected to PU).
Hu fails to teach they formed on a base substrate.
Du teaches (Du, Fig. 5B, ie Input lines EML, GL, RCL on substrate 1, Fig. 7B, T1, T2 etc.).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hu and Du before him before the effective filing date of the claimed invention, to modify the shift register taught by Hu to include the manufacturing method of Du in order to obtain a shift register formed on a base substrate with multiple interconnected layers. One would have been motivated to make such a combination because it reduces the are required for the circuit by using known methods of multilayer circuit fabrication.
In regards to dependent claim 39, Hu teaches a display device comprising the display substrate according to claim 1 (Hu, [0087]).
Allowable Subject Matter
Claims 2-3,5,7-10,14-15,18,20,23,25,28,30, and 32-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST.
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812