Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1-3, 5-7, 12, 13, 17, 19-20,22-25, 28-30 , 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dasgupta et al. (hereinafter Dasgupta, US 2017/0236704). In regards to independent claim 1, Dasgupta teaches a semiconductor substrate comprising: a template substrate including a main substrate (105) , a first seed portion (416) , and a second seed portion (trench adjacent to 416) (Dasgupta, Fig. 4A) , a first semiconductor part in contact with the first seed portion (130A) and a second semiconductor part in contact with the second seed portion (130B) (Dasgupta, Fig. 4A) , wherein the first semiconductor part and the second semiconductor part include a nitride semiconductor ([0035], Elevated III-N semiconductor structure , [0028], the III-N material system (e.g., AlN , GaN , AlGaN , InAlGaN , etc.) ) and are adjacent to each other in an a-axis direction of the nitride semiconductor (Adjacent to Y-axis on Fig. 4A, Fig. 3A shows the y axis to be the <11-20> axis, which is the a-axis in specification of the current application), , and the first semiconductor part comprises a first lower edge along an m-axis direction of the nitride semiconductor (Fig. 4A, 417, lower edge is sidewall in contact with the trench, m-axis is the x-axis on Fig. 4A, Fig. 3A shows the x-axis to be the <1-100>, which is the m-axis in specification of the current application) , and a first protruding portion protruding toward the second semiconductor part side farther than the first lower edge (405) (Dasgupta, Fig. 4A) . In regards to dependent claim 2 , Dasgupta teaches t he semiconductor substrate according to claim 1, wherein the template substrate further includes a mask pattern comprising a first opening portion and a second opening portion adjacent to each other in a first direction, and a mask portion located between the first opening portion and the second opening portion (Dasgupta, Fig. 4A, 416 repeats on the y axis) , the first lower edge is located between a mask-portion center and the first opening portion in a plan view (Dasgupta, Fig. 4A, 417) , and the second semiconductor part comprises a second lower edge located between the mask-portion center and the second opening portion in a plan view, and a second protruding portion protruding toward the first semiconductor part side farther than the second lower edge in a plan view (Dasgupta, Fig. 4A, 405 ) . In regards to dependent claim 3 , Dasgupta teaches wherein the first semiconductor part comprises a first upper edge located between the mask-portion center and the first opening portion in a plan view (Dasgupta, Fig. 5B). , and in the first direction, a maximum distance between the first opening portion and the first protruding portion is larger than a distance between the first opening portion and the first upper edge (Dasgupta, Fig. 5B) . In regards to dependent claim 5 , Dasgupta teaches wherein a side surface of the first semiconductor part comprises a lower inclined surface comprising the first lower edge, and an upper inclined surface comprising the first upper edge (Dasgupta, Fig. 5B) . In regards to dependent claim 6 , Dasgupta teaches wherein a first acute angle formed by the lower inclined surface and a plane perpendicular to the first direction is smaller than a second acute angle formed by the upper inclined surface and a plane perpendicular to the first direction (Dasgupta, [0084]). In regards to dependent claim 7 , Dasgupta teaches wherein the first acute angle is 12° or less. (Dasgupta, [0084]). In regards to dependent claim 1 2, Dasgupta teaches wherein the first semiconductor part comprises a first upper edge located between the mask-portion center and the first opening portion in a plan view, and the first upper edge is a top portion of the first protruding portion (Dasgupta, Fig. 5B) . In regards to dependent claim 13 , Dasgupta teaches wherein the second semiconductor part comprises a second upper edge located between the mask-portion center and the second opening portion in a plan view, and the second upper edge is a top portion of the second protruding portion (Dasgupta, Fig. 5B) . In regards to dependent claim 17 , Dasgupta teaches wherein an upper interval indicating an interval between the first upper edge and the second upper edge is less than 5 μm (Dasgupta, [0042]) . In regards to dependent claim 19 , Dasgupta teaches wherein a ratio of a lower interval, which indicates an interval between the first lower edge and the second lower edge, to a width of the mask portion is less than 0.7 (Dasgupta, [0038] Fig. 6A) . In regards to dependent claim 2 0 , Dasgupta teaches a plane comprising the first upper edge and the first lower edge forms an angle of 12° or less with respect to a plane perpendicular to the first direction (Dasgupta, [0084]) . In regards to dependent claim 2 2 , Dasgupta teaches wherein a first function layer is arranged in a layer above the first semiconductor part. (Dasgupta, Fig. 5D) In regards to dependent claim 2 3 , Dasgupta teaches wherein the first function layer comprises an active layer, and the active layer does not extend to the first lower edge (Dasgupta, Fig. 5D) . In regards to dependent claim 2 4 , Dasgupta teaches wherein a second function layer is arranged in a layer above the second semiconductor part, and wherein the first function layer and the second function layer are isolated from each other (Dasgupta, Fig. 4D) . In regards to dependent claim 2 5 , Dasgupta teaches wherein the first function layer comprises a GaN -based p-type semiconductor layer, and the mask pattern comprises a silicon oxide film and/or a silicon nitride film (Dasgupta, [0030], [0028]) . I n regards to dependent claim 2 8 , Dasgupta teaches wherein the first semiconductor part comprises a low-defect portion overlapping the mask portion in a plan view, and the low-defect portion has a threading dislocation density of 5×106 [pieces/cm2] or less, and a size of the low-defect portion in the first direction is 10 μm or larger. ([0041], “ In an exemplary embodiment, top surface 438 has a surface defect density (e.g., measured as etch pits/cm.sup.2 or by plan-view TEM measurements) that is at least an order or magnitude lower than that of inclined sidewall facet 405 ,” The defects on the sidewall facet are non-threading as they are misfit dislocations are parallel to the interface. A cross section parallel to the <0001> or z-axis would include the misfit dislocations that are on the sidewall facet as they are perpendicular to the z axis). In regards to dependent claim 2 9 , Dasgupta teaches wherein the first semiconductor part comprises a low-defect portion overlapping the mask portion in a plan view, and in the low-defect portion, a non-threading dislocation density in a cross section parallel to a thickness direction is larger than a threading dislocation density in an upper surface ([0041], “ In an exemplary embodiment, top surface 438 has a surface defect density (e.g., measured as etch pits/cm.sup.2 or by plan-view TEM measurements) that is at least an order or magnitude lower than that of inclined sidewall facet 405 ,” The defects on the sidewall facet are non-threading as they are misfit dislocations are parallel to the interface. A cross section parallel to the <0001> or z-axis would include the misfit dislocations that are on the sidewall facet as they are perpendicular to the z axis). In regards to dependent claim 30 , Dasgupta teaches wherein the first semiconductor part comprises a nitride semiconductor, and the main substrate is a heterogeneous substrate different from the nitride semiconductor in terms of lattice constant (Dasgupta, [0029-0029]) . In regards to in dependent claim 3 2 , Dasgupta teaches a GaN -based crystal body comprising a GaN -based semiconductor ([0035], Elevated III-N semiconductor structure , [0028], the III-N material system (e.g., AlN , GaN , AlGaN , InAlGaN , etc.) ) and having an upper surface and a lower surface parallel to a (0001) plane (Top and bottom surface of 130A which are parallel to the (0001) plane on Fig. 4A and Fig. 3A) , the GaN -based crystal body comprising: a lower edge parallel to a <1-100> direction (Fig. 4A, 417, lower edge is sidewall in contact with the trench, m-axis is the x-axis on Fig. 4A, Fig. 3A shows the x-axis to be the <1-100> direction), and a protruding portion protruding in a <11-20> direction farther than the lower edge (405, Fig. 3A shows the y-axis to be the <11-20> direction) (Dasgupta, Fig. 4A) , wherein a non-threading dislocation density in a cross section parallel to a <0001> direction is larger than a threading dislocation density in the upper surface ([0041], “ In an exemplary embodiment, top surface 438 has a surface defect density (e.g., measured as etch pits/cm.sup.2 or by plan-view TEM measurements) that is at least an order or magnitude lower than that of inclined sidewall facet 405 ,” The defects on the sidewall facet are non-threading as they are misfit dislocations are parallel to the interface. A cross section parallel to the <0001> or z-axis would include the misfit dislocations that are on the sidewall facet as they are perpendicular to the z axis) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 36 is/are rejected under 35 U.S.C. 103 as being obvious over Dasgupta in view of Kamikawa et al. (hereinafter Kamikawa , US 2023/0127257). The applied reference has a common joint inventer with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). FILLIN "Insert an explanation of obviousness. See MPEP § 2144." \d "[ 4 ]" This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. In regards to dependent claim 36, Kamikawa teaches : growing the first and second semiconductor parts each including a group III nitride semiconductor by an ELO method at a V/III ratio of less than 1000 ( Kamikawa , [0020]) . It would have been obvious to one of ordinary skill in the art, having the teachings of Dasgupta and Kamikawa before him before the effective filing date of the claimed invention, to modify the GaN crystal film taught by Dasgupta to include the ELO method of Kamikawa in order to obtain a GaN crystal grown using the ELO method . One would have been motivated to make such a combination because it enables high speed lateral growth of crystal GaN . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT WILLIAM C TRAPANESE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3304 . 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To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/ Primary Examiner, Art Unit 2812