DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Claims 1-19 are currently pending.
Independent claim(s) 1 and 18 and dependent claims 2-3, 7-8, and 15-16 have been amended by applicant’s amendments received 25 June 2026. Claim 19 has been newly added. No new matter has been introduced.
Prior objections of the drawings have been overcome by amendment and are therefore withdrawn.
Prior objections of claims 2, 15 and 16 have been overcome by amendment and are therefore withdrawn.
Prior rejections of claims 3, 7 and 8 (and therefore claims 3-14) under USC § 112(b) have been overcome by amendment and/or explanation by Applicant, and are therefore withdrawn.
Response to Arguments
Applicant's arguments filed 25 June 2026 have been fully considered but they are not persuasive. Applicant's arguments are directed to the point that the reference (Oka, US 20190297287 A1) fails to show certain features of the invention, specifically a causal sequence where a predetermined control signal pattern is applied to control a light receiver, which outputs an output signal which is evaluated for failure (Remarks, pg. 11), as Oka is a monitoring-based failure detection approach. However, the limitation as written which requires a light reception unit to be controlled based on a predetermined pattern of a control signal is broad in its definition, and the system of Oka includes a control unit which sets specific pixel addresses for a pixel array to readout and then compares those readout values to a predetermined value to determine failure of components within the array. Oka, in paragraphs [0130] – [0135], for example, describes where the control unit (121), and row drive unit (102) of Figs. 5, 6 operate a readout procedure of the pixel array (101) based on row and/or column addresses via control lines, wherein the readout is used to determine failures. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As ‘pattern’ in the claims is not more explicitly limiting, a preset grouping of rows, columns, or a combination resulting in pixel addresses would be considered a readout pattern.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Oka et al. (hereinafter Oka, US 20190297287 A1).
Regarding claims 1, 18 and 19, Oka anticipates a photodetection device, a distance measuring system, and a photodetection device with a plurality of light reception elements wherein the photodetection device comprises:
a light reception unit that includes a pixel array unit including light reception elements aligned in a matrix ([0014]; Fig. 4, pixel array (101));
a control signal generation unit that generates a control signal ([0133], [0154] - [0157]; Fig. 5 control unit (121) supplies a control signal);
a control unit that is electrically connected with the light reception unit via a control line and controls the light reception unit based on the control signal ([0133], [0154] - [0157]; Fig. 5 control unit (121) supplies a control signal, is connected to pixel array (101) via lines such as TCVs and control line gate (143));
a processing unit that is electrically connected with the light reception unit via a signal line and processes an output signal from the light reception unit ([0129], [0138] - [0152]; Fig. 5 includes image signal output unit (103) and image processing unit (122) to process images collected);
and a failure determination unit that detects a failure,
wherein the failure determination unit detects a failure of the control line from the output signal from the light reception unit, the light reception unit being controlled based on a failure detection control signal having a predetermined pattern ([0116], [0130] - [0134], [0143] - [0147], [0250], [0262]; Fig. 5, failure detector (124) determines failures in control lines, ADC+TCVs and other processes, and may determine failure based on signals collected for predetermined pixel addresses from the pixel array (101), where outputs of the pixel array (101) may be compared to predetermined pixel values),
and where the distance measurement system of claim 18 further comprises:
a lighting device that emits irradiation light ([0107], [0455], [0605], [0635]; Fig. 1, where headlamp (34) may emit in connection with other processes);
and a photodetection device that receives reflected light obtained when the irradiation light is reflected by a subject ([0455], [0655]; where system uses imaging units to acquire distance information on objects in an environment based on collected light) wherein the photodetection device is as claimed in claim 1.
Regarding claim 2, Oka anticipates the photodetection device according to claim 1 wherein
Each of the light reception elements respectively includes an avalanche photodiode ([0009]; where pixels within array are photodiodes, where avalanche photodiodes are a well-known variant of photodiode used in image sensing).
Regarding claim 3, Oka anticipates the photodetection device according to claim 1 wherein each of the light reception elements includes
a driving switch that drives the light reception element ([0127] - [0132]; Figs. 5, 19 drive unit (102, 272) drives each pixel (221)),
an output switch that controls output of an output signal from the light reception element ([0270] - [0276]; Figs. 5, 18, 19, where pixels (221) have selection transistors (235) which cause pixel output along VSLs),
and further comprising: a logical add circuit that provides an output according to the output signal from each of the light reception elements ([0143], [0280] - [0284; Figs. 5, 18, image signal output (103) and processing unit (122) work in addition to comparator (261) and counter (262) for signal collection and output).
Regarding claim 4, Oka anticipates the photodetection device according to claim 3 wherein
the control unit includes a horizontal control unit that controls the light reception elements in units of columns, and a vertical control unit that controls the light reception elements in units of rows ([0281] - [0288]; Fig. 19, where columns are controlled along lines (281-1)…), rows along lines (282-1…), and controlled by row drive units (272) and column scan circuits (275-1, 275-2)).
Regarding claim 5, Oka anticipates the photodetection device according to claim 4 wherein
a first control line that electrically connects the vertical control unit and the driving switch ([0127] - [0134]; Figs. 5, 19, TCV (93-1) connects row drive unit (102) to pixels (221) in given rows),
a second control line that electrically connects the vertical control unit and the output switch ([0127] - [0134]; Figs. 5, 19, TCV (93-2) connects outputs (102) of pixels (221) in given rows to image signal output unit (103)),
a third control line that electrically connects the horizontal control unit and the driving switch ([0127] - [0134], [0287] - [0298]; Figs. 5, 19, column signal lines (281-1...) connects column scan circuit (275-1) to pixels (221) in given columns),
a fourth control line that electrically connects the horizontal control unit and the output switch ([0127] - [0134], [0287] - [0298]; Figs. 5, 19, TCVs (93-11...) connects pixels (221) in given columns to column ADC),
and a fifth control line that electrically connects the vertical control unit and the logical add circuit ([0127] - [0134], [0287] - [0298]; Figs. 5, 19, TCVs (93-1) and (93-11, 93-12) connect row drive unit (102) to image signal output unit (103) and image processing unit (122)).
Regarding claim 15, Oka anticipates the photodetection device according to claim 1 wherein
the failure determination unit outputs a predetermined signal to an output terminal or a host computer when the failure is detected ([0151], [0607]; Fig. 51, where the system may output image information to a monitor (2007) which may occur after signal processing and failure detection).
Regarding claims 16 and 17, Oka anticipates the photodetection device according to claim 1 wherein
The photodetection device is formed by a first substrate on which the pixel array unit is provided, and a second substrate that is stacked on the first substrate and provided with the control unit, the processing unit, and the failure determination unit,
wherein the control line is provided on the second substrate ([0411] - [0422]; Figs. 32-36 show multiple variations where components such as the pixel array (511) exist on a separate substrate than the control lines, such as TSVs, comparator (541), drive unit (522) and failure detector (521)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (hereinafter Oka, US 20190297287 A1) in view of Feekes (US 20200084437 A1).
Regarding claim 6, Oka teaches the photodetection device according to claim 5, but does not explicitly mention a circuit for digital signal processing such as downsampling.
Feekes teaches a system and method for operating image sensors which may include fault detection circuitry, and where the data processing unit includes a downsampling circuit ([0026], where image processing circuitries can include compression circuits, error correction circuits or subsampling circuits).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Oka to incorporate the teachings of Feekes to incorporate image/data processing circuits such as a downsampling or subsampling circuit with a reasonable expectation of success. Data processing of these kinds is well known in the art of image sensors used for object detection and tracking, and integration of a processing circuit as taught by Feekes would have a predictable result of reducing processing time and allocation. Additionally, Feekes notes that integration of fault detection functionalities reduces the cost of systems over those with redundant circuitry ([0001] – [0002]).
Regarding claim 7, Oka as modified above teaches the photodetection device according to claim 6, wherein
the control signal generation unit outputs the failure detection control signal during a period in which a frame synchronization signal for image acquisition is not asserted ([0111] - [0112], [0282] - [0284], [0326]; Fig. 24, where the system may stop the image process when a failure has met, and failure checking may be completed in synchronization with clock signals).
Regarding claim 8, Oka as modified above teaches the photodetection device according to claim 7, wherein
a processing unit failure detection signal for detecting a failure of the processing unit ([0297] - [0302]; Fig. 18, where ADC and TCV failure detector (271) can detect failures in ADCs which will affect processing of signals from imaging device (72)),
and a control line failure detection signal for detecting the failure of the control line are sequentially included in the failure detection control signal ([0116], [0254] - [0263], [0301] – [0333]; Fig. 16 where failure detector (124) may include pixel control line failure detector (202), and failure operation tests, pixel control tests and signal line failure detection may be performed sequentially during indicated periods such as blanking periods, and where the sequence may be switched).
Regarding claim 9, Oka as modified above teaches the photodetection device according to claim 8, wherein
before or after the control line failure detection signal, a light reception unit failure detection signal for detecting a failure of the light reception unit is included in the failure detection control signal ([0116], [0160], [0306]; Figs. 12, 15 where the pulse output failure detector (142) determines if signals from latches within the pixel are high or low and therefore have a failure).
Regarding claims 10-12, Oka as modified above teaches the photodetection device according to claims 9-11, respectively, wherein
the control line failure detection signal includes a first signal for detecting a failure of the fifth control line,
the control line failure detection signal includes a second signal for detecting failures of the second and fourth control lines, and
the control line failure detection signal includes a third signal for detecting failures of the first and third control lines ([0250] - [0264]; where pixel control line failure detector (202) within failure detector (124) may determine failures in control lines (L), TCVs such as (93-1, 93-2, 93-11, 93-12), and other control lines such as signal lines (281-1) and will inherently supply a signal for failure detection in each signal line).
Regarding claim 13, Oka as modified above teaches the photodetection device according to claim 12, but does not explicitly teach determining a failure of the digital signal processing circuits such as a downsampling circuit.
Feekes teaches a system and method for operating image sensors which may include fault detection circuitry, and where the data processing unit includes a downsampling circuit ([0026]), and further teaches a system which detects a failure of the downsampling circuit ([0026] - [0029], [0037]; Fig. 4 where system's fault detector circuitry (106) may provide a fault signal in response to determining an error with one or more processing circuitries (104)).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Oka to incorporate the teachings of Feekes to incorporate image/data processing circuits such as a downsampling or subsampling circuit, where the processing circuit includes a way of fault detection, with a reasonable expectation of success. Data processing of these kinds is well known in the art of image sensors used for object detection and tracking, and integration of a processing circuit as taught by Feekes would have a predictable result of reducing processing time and allocation. Additionally, Feekes notes that integration of fault detection functionalities reduces the cost of systems over those with redundant circuitry ([0001] – [0002]).
Regarding claim 14, Oka as modified above teaches the photodetection device according to claim 13, but does not explicitly discuss the order in which signals are included in the control line failure detection signal.
Feekes teaches a system and method for operating image sensors which may include fault detection circuitry, and where the data processing unit determines signals and a process which includes multiple signals from multiple fault detections ([0043] - [0049]; Fig. 6,which shows a flowchart for operating an imaging system, which includes fault detection but where, if desired, the order of steps may be changed, or one or more additional steps may be added to include other processing circuity).
Therefore, to one of ordinary skill in the art before the effective filing date of the claimed invention, it would have been obvious prima facie to modify Oka to incorporate the teachings of Feekes to choose an order of operation for outputting the failure detection signals with a reasonable expectation of success. As noted above, Feekes teaches that the number of steps involved is reflective of the number of pipeline processing circuitry and therefore fundamentally, the order of operations in fault detection are flexible. The order of the failure signal outputs, as it does not have a meaningful impact on the inventive idea, is patently the same thing as is claimed. Additionally, the instant application agrees with the teaches of Feekes, by noting that while sequentially checking for failures is important, “the order is not limited to the order illustrated in FIG. 11, and the order may be changed.” ([0078]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 9055249 B2) teaches a system for correcting a column line failure in an imager, which includes a pixel selection circuit and is configured to provide a pixel output signal, while potentially modifying output signals based on column failure detection.
Kobayashi et al. (US 20200412992 A1) teaches a photoelectric conversion apparatus which includes a pixel array, such as a CMOS image sensor, where the system includes failure checks within the array circuitry and modifies outputs or signals based on failure of specific components.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kara Richter whose telephone number is (571)272-2763. The examiner can normally be reached Monday - Thursday, 8A-5P EST, Fridays are variable.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.M.R./Examiner, Art Unit 3645
/HELAL A ALGAHAIM/SPE , Art Unit 3645
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