DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The Japanese parent application as required by 37 CFR 1.55 has been filed on 02/18/2026 is considered and entered.
Response to Amendment
The Amendment with respect to claims 1-3, 5-6, 8, and 12-18, filed on 02/10/2026 have been considered for examination based on their merits. The original claims 4, 7, and 9-11 have been considered.
Response to Arguments
Applicant's arguments (see Remarks, pages 9-12) filed 02/10/2026 have been fully considered but they are not persuasive for the following reasons with respect to claim 1.
Regarding Independent Claim 1. The Applicant argues (see Remarks, page 9) that NARUMI does not disclose or suggest the claim 1 feature, “an electric field relaxation section in a lower part of the side surface of the fin to relax electric field concentration.” The Examiner carefully reviewed the NARUMI prior art (Figure 3) and the Figure 1A of the instant application. With respect to the “lower part of the side surface of the fin”, apparently, the above arguments are not persuasive as it is evidenced that the comparative figures below show no difference between the annotated drawings, Figure 1A, element 116A of the instant application with Figure 23, element HK of the NARUMI art. The HK in the prior art is apparently present at the lower part of the side surfaces of the fin, F, as exemplified in various embodiment, as demonstrated in other drawings as well, for example, Figures 3, 17, 25, 27, 31, 36, and 38.
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The Applicant further argues (see Remarks, page 9) that the NARUMI art discloses a highly directional film formation method, a thick film is deposited over the top of the fin, F and top of the element isolation region, 103, each top being a flat portion, while a thin film is deposited over each side surface of the Fin, F as per the drawing, Figure 23. The Examiner considers this argument, but are not persuasive. Figure 23, as annotated below, shows the difference between the flat portion and the lower part of the side surface portion of the fin, F, and clearly shows the thickness of the HK film (t3) on the lower part of the side surfaces of the fin, F, is greater than the thickness of the upper part side surfaces (t2) of the fin, F.
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The Applicant further argues (see Remarks, page 10) that NARUMI art teaches away from forming high dielectric constant film HK on the side surfaces of the fin, F, due to the removal of the HK film by isotropical etching as cited in the paragraphs [102-103]. The Examiner considers this argument, but is not persuasive for the following facts. According to paragraph [103], the HK film has been removed at the regions of thin film portions, labeled as t2 and not at the portions, labeled as t3 and annotated above as the lower part of the side surfaces of the fin, F.
Regarding Dependent Claims 2-18. Claims 2–18 depend on claim 1 and therefore follow the above similar discussions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over TAYANAKA (prior art used in the previous OA), in view of SHIMIZU (prior art used in the previous OA), and NARUMI (prior art used in the previous OA).
Regarding Claim 1, TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), comprising:
a first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]);
a transistor (Fig. 41, RST/TG, pixel transistors, [0268]) including a fin (Figs. 20/21/25/42, finFET transistor, [0280]) to stand on a main surface section of the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]), a first main electrode (Fig. 41, a part of “N—” region of the first semiconductor substrate, 21 that is held in contact with the lower side in the figure of the gate terminal is a “source terminal”, [0143]), a channel-forming region (a channel of the transistor is formed in the portion from the source terminal to the drain terminal in the gate terminal, [0143]), a second main electrode (Fig. 41, a part of “N” region of the second semiconductor substrate, 22, that is held in contact with the left side of the upper side in the figure of the gate terminal is a “drain terminal”, [0143]), a gate insulating film (Figs. 15/39/40, 21a, gate oxide film, [0175]), and a gate electrode (Figs. 15/40, a part of the polysilicon is removed by etching, and the “gate terminal” of the TG and the “gate terminal” of the RST are obtained, [0176]).
TAYANAKA does not explicitly disclose a solid-state imaging device comprising: wherein the first main electrode, the channel-forming region, and the second main electrode are in the fin along a channel length direction, and the gate insulating film and the gate electrode covers an upper surface and a side surface of the fin to extend over the fin along a channel width direction.
SHIMIZU teaches a solid-state imaging device (Figs. 5/7, MOSFET with a fin structure, [0133]) comprising:
the first main electrode (Figs. 5/7, 12, source electrode), the channel-forming region (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]), and the second main electrode (Figs. 5/7, 14, drain electrode) are in the fin (Figs. 5/7, 100/200, vertical transistor is a MOSFET with a fin structure, [0133]) along a channel (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]) length direction (Figs. 2/5, first direction), and
the gate insulating film (Figs. 2/5/7, 18a/18b/18c/24, first/second/third gate insulating layer/interlayer insulating layer) and the gate electrode (Figs. 2/5/7, 20a/20b/20c, first/second/third/ gate electrode) covers an upper surface and a side surface of the fin to extend over the fin along a channel (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]) width direction (Figs. 2/7, second direction); and
an electric field relaxation section (Figs. 4/5/7, 38a/38b/38c, electric field relaxation region, [0120]) provided in a lower part of the side surface of the fin ([0120]) to relax electric field concentration ([0074-0078]).
Though SHIMIZU teaches an electric field relaxation section under the gate insulating layer, TAYANAKA as modified by SHIMIZU does not explicitly disclose a solid state imaging device comprising: an electric field relaxation section provided in a lower part of the side surface of the fin to relax electric field concentration.
NARUMI teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]) comprising: an electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) in a lower part of the side surface (annotated Figure 23 and compared with the annotated Figure 1A of the instant application) of the fin (Fig. 23, F, [0066]) to relax electric field concentration ([0066], [0100], [0141], [0159], [0179]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have TAYANAKA as modified by SHIMIZU to incorporate the teachings of NARUMI, such that a solid state imaging device comprising: an electric field relaxation section in a lower part of the side surface of the fin to relax electric field concentration, so that this arrangement leading to an improvement in disturbance characteristics. Furthermore, erase/write endurance characteristics and retention characteristics can be improved by the high dielectric constant film, HK (NARUMI, [0066], [0159]).
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Regarding Claim 2, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
TAYANAKA further teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), further comprising:
a second semiconductor layer (Fig. 41, 21, first semiconductor substrate [0268]) stacked on the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]); and
a plurality of pixels (Fig. 1, a region corresponding to an area of one “pixel” formed on a semiconductor substrate having a planar structure, [0123]; plurality of pixels, [0130]), wherein
each of the plurality of pixels (Fig. 1, a region corresponding to an area of one “pixel” formed on a semiconductor substrate having a planar structure, [0123]; plurality of pixels, [0130]) includes a photoelectric conversion element (Figs. 41/45, PD, photodiode, [0284]) on a main surface section of the second semiconductor layer (Fig. 41, 21, first semiconductor substrate [0268]) on a side opposite to a side of the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]), the pixels is coupled to the transistor (the PD of the first semiconductor substrate, 21, and the FD of the second semiconductor substrate, 22 are electrically connected by the TG transistor [0185]), and
the transistor is an amplification transistor that constitutes part of a pixel circuit (Figs. 20/21/25/41/42, each pixel of the image sensor, 10 is configured to transfer charges accumulated in a photodiode to a floating diffusion (FD) via an AMP, amplifying transistor, [0125]).
Regarding Claim 3, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
SHIMIZU further teaches a solid-state imaging device (Figs. 5/7, MOSFET with a fin structure, [0133]), wherein
the fin (Figs. 5/7, 100/200, vertical transistor is a MOSFET with a fin structure, [0133]) corresponds to a groove dug down (Fig. 5, 16a/16b/16c, first/second/third trench, [0026], [0031]) from a main surface (Fig. 5, 36, JFET region [0115]) of the first semiconductor layer (Fig. 5, 10, silicon carbide layer, [0031]) along a thickness direction (annotated Figure 5), and
the electric field relaxation section (Fig. 5, 38a/38b/38c, field relaxation region, [0079]) is provided in a bottom of the groove (Fig. 5, 16a/16b/16c, first/second/third trench, [0026], [0031], [0079]).
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NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the fin (Figs. 28, fin F, [0066]) is formed by a groove dug down (Fig. 28, 103, element isolation trench, [0160]) from a main surface (Fig. 28, MA, memory cell region, [0162]) of the first semiconductor layer (Fig. 28, 100, semiconductor substrate) along a thickness direction (Fig. 28, Z- direction), and
the electric field relaxation section (Figs. 3/30, HK, a high dielectric constant film, [0065-0066], [0164-0165]) is provided in a bottom of the groove (Fig. 28, 103, element isolation trench, [0160]).
Regarding Claim 4, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 3.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) includes an insulator having a higher dielectric constant than silicon oxide (an Al2O3 film, a HfO film, a Ta2O5 film, a SiTiO3 film, a HfSiO film, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]).
Regarding Claim 5, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) includes the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]) and the insulator (Figs. 14/15, ONO insulating film, [0115]) on the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]).
Regarding Claim 6, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator (Figs. 14/15, ONO insulating film, [0115]) includes a first insulator (Fig. 15, 107, middle insulating film (includes a silicon nitride film), [0163]) and a second insulator (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) on the first insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]), and the second insulator (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) has a dielectric constant lower than a dielectric constant (note: according to Wikipedia, https://www.en.wikipedia.org/wiki/Relative_permitivity, the dielectric constant of silicon dioxide (3.9) is lower than the dielectric constant of silicon nitride (7-8)) the first insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]).
Regarding Claim 7, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator has a dielectric constant that gradually becomes lower from the bottom of the groove toward an opening of the groove (annotated Figure 16).
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Regarding Claim 8, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) includes a first silicon oxide film (Fig. 15, 106, lower insulating film (includes a silicon nitride film), [0163]) and the insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]) on the first silicon oxide film (Fig. 15, 106, lower insulating film (includes a silicon nitride film), [0163]).
Regarding Claim 9, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) further includes a second silicon oxide film (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) on the insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]).
Regarding Claim 10, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator is silicon oxide or aluminum oxynitride (an Al2O3 film, a HfO film, a Ta2O5 film, a SiTiO3 film, a HfSiO film, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]).
TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), wherein
the insulator is silicon oxide or aluminum oxynitride (as the oxide film, in order to further reduce the gate leak, a hafnium oxide film, a zirconium oxide film, or the like may be used; as the oxynitride film, a silicon oxynitride film, a hafnium oxynitride film, a zirconium oxynitride film, or the like may be used, in such a manner, a high dielectric film can be used, [133]).
It should be noted that substituting (silicon oxide or aluminum oxynitride) for (hafnium oxide or hafnium oxynitride) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 11, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is a silicon oxynitride film (Fig. 3, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]; 108, upper insulating film, includes a silicon oxynitride film, [0063]) that is nitride (Fig. 3, 107, middle insulating film includes a silicon nitride, [0063]) of the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]).
TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is a silicon oxynitride film (as the oxynitride film, a silicon oxynitride film, a hafnium oxynitride film, a zirconium oxynitride film, or the like may be used, in such a manner, a high dielectric film can be used, [133]) that is nitride of the gate insulating film (Fig. 15A, 132, the insulating film, an oxide or a nitride film is used, [0143]).
Regarding Claim 12, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator of the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is thicker (Figs. 3/15, a thick film is deposited over the top of the fin F and top of the element isolation region, 103, [0102]; Fig. 23, the thick film over the top of the element isolation region, 103 has a thickness, t3; t3>t2, [0144-0145]) than the insulator in a region other than the electric field relaxation section (Figs. 3/15, a thin film is deposited over each side surface of the fin F, [0102]; the think film over the side surface of the fin F has a thickness, t2, [0144-0145]).
Regarding Claim 13, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the gate electrode (Fig. 21, MG, memory gate electrode, [0172]) includes metal (metal silicide film, [0172]).
Regarding Claim 14, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the gate electrode (Fig. 21, 105, CG/GE, control gate electrode, [0114]) includes polycrystalline silicon (Fig. 21, polysilicon film, 105, CG/GE, [0113]) doped with an impurity that decreases a resistance value (Fig. 19, the metal silicide film, SIL can reduce the diffusion resistance or the control resistance, [0126], [132]), and
a density of the impurity doped into the gate electrode (Fig. 21, 119a/111a, n- type semiconductor region, [0124]) is lower in a portion of the gate electrode (Fig. 21, CG, 105, control gate) adjacent to the electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) than in remaining portions of the gate electrode (Fig. 21, 119b/111b, n+ type semiconductor region, [0124]).
Regarding Claim 15, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the density of the impurity (Fig. 21, 119b/111b, n+ type semiconductor region, [0124]) gradually decreases toward a bottom of an inside of a groove (Fig. 21, 119a/111a, n- type semiconductor region, [0124]).
Regarding Claim 16, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) comprises the gate electrode (Fig. 21, 105, CG, control gate electrode, [0114]) not doped with the impurity (Fig. 21, 109, conductive film of the memory gate (MG), [0119]).
Regarding Claim 17, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is in an area up to 20% of a height of the fin (annotated Figure 27).
Regarding Claim 18, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is on a side of, of the first main electrode (Fig. 21, 111a/111b, MS, source region, [0124-0132]) and the second main electrode, one used as a drain region (Fig. 21, 119a/119b, MD, source region, [0124-0132]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150145023 A1 – Figure 32
STATEMENT OF RELEVANCE – High-K insulating film, 114, and the low-K silicon oxide film, 113 as electric field relaxation section of the finFET ([0186]).
US 20180226489 A1 – Figure 25
STATEMENT OF RELEVANCE – Gate dielectric layer, 200, can be an insulating dielectric layer, for example, a silicon oxide, and can be a high-K dielectric material, ([0125]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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