DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, the Applicant has not filed a certified copy of Japanese parent application as required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/16/2023 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Preliminary Amendment
The Preliminary Amendment with respect to “Amendments to the Specification”, filed on 10/16/2023 has been considered and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Tayanaka et al, (hereinafter TAYANAKA), US 20160204153 A1, in view of Tatsuo Shimizu, (hereinafter SHIMIZU), US 20200303494 A1, and further in view of Shunichi Narumi, (hereinafter NARUMI), US 20180182774 A1.
Regarding Claim 1, TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor) comprising:
a first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]);
a transistor (Fig. 41, RST/TG, pixel transistors, [0268]) including a fin (Figs. 20/21/25/42, finFET transistor, [0280]) provided to stand on a main surface section of the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]), a first main electrode (Fig. 41, a part of “N—” region of the first semiconductor substrate, 21 that is held in contact with the lower side in the figure of the gate terminal is a “source terminal”, [0143]), a channel-forming region (a channel of the transistor is formed in the portion from the source terminal to the drain terminal in the gate terminal, [0143]), a second main electrode (Fig. 41, a part of “N” region of the second semiconductor substrate, 22, that is held in contact with the left side of the upper side in the figure of the gate terminal is a “drain terminal”, [0143]), a gate insulating film (Figs. 15/39/40, 21a, gate oxide film, [0175]), and a gate electrode (Figs. 15/40, a part of the polysilicon is removed by etching, and the “gate terminal” of the TG and the “gate terminal” of the RST are obtained, [0176]),
TAYANAKA does not explicitly disclose a solid-state imaging device comprising: the first main electrode, the channel-forming region, and the second main electrode being provided in the fin along a channel length direction, the gate insulating film and the gate electrode covering an upper surface and a side surface of the fin to extend over the fin along a channel width direction.
SHIMIZU teaches a solid-state imaging device (Figs. 5/7, MOSFET with a fin structure, [0133]) comprising:
the first main electrode (Figs. 5/7, 12, source electrode), the channel-forming region (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]), and the second main electrode (Figs. 5/7, 14, drain electrode) being provided in the fin (Figs. 5/7, 100/200, vertical transistor is a MOSFET with a fin structure, [0133]) along a channel (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]) length direction (Figs. 2/5, first direction),
the gate insulating film (Figs. 2/5/7, 18a/18b/18c/24, first/second/third gate insulating layer/interlayer insulating layer) and the gate electrode (Figs. 2/5/7, 20a/20b/20c, first/second/third/ gate electrode) covering an upper surface and a side surface of the fin to extend over the fin along a channel (Figs. 2/7, 30a/30b, first or second p-well region functions as a channel region, [0047], [0050]) width direction (Figs. 2/7, second direction); and
an electric field relaxation section (Figs. 4/5/7, 38a/38b/38c, electric field relaxation region, [0120]) provided in a lower part of the side surface of the fin ([0120]) to relax electric field concentration ([0074-0078]).
Though SHIMIZU teaches an electric field relaxation section under the gate insulating layer, TAYANAKA as modified by SHIMIZU does not explicitly disclose a solid state imaging device comprising: an electric field relaxation section provided in a lower part of the side surface of the fin to relax electric field concentration.
NARUMI teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]) comprising: an electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) provided in a lower part of the side surface (annotated Figure 3) of the fin (Fig. 3, F, [0066]) to relax electric field concentration ([0066], [0100], [0141], [0159], [0179]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have TAYANAKA as modified by SHIMIZU to incorporate the teachings of NARUMI, such that a solid state imaging device comprising: an electric field relaxation section provided in a lower part of the side surface of the fin to relax electric field concentration, so that this arrangement leading to an improvement in disturbance characteristics. Furthermore, erase/write endurance characteristics and retention characteristics can be improved by the high dielectric constant film, HK (NARUMI, [0066], [0159]).
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Regarding Claim 2, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), further comprising:
a second semiconductor layer (Fig. 41, 21, first semiconductor substrate [0268]) stacked on the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]); and
pixels (Fig. 1, a region corresponding to an area of one “pixel” formed on a semiconductor substrate having a planar structure, [0123]) each including a photoelectric conversion element (Figs. 41/45, PD, photodiode, [0284]) provided on a main surface section of the second semiconductor layer (Fig. 41, 21, first semiconductor substrate [0268]) on a side opposite to a side of the first semiconductor layer (Fig. 41, 22, second semiconductor substrate [0268]), the pixels being coupled to the transistor (the PD of the first semiconductor substrate, 21, and the FD of the second semiconductor substrate, 22 are electrically connected by the TG transistor [0185]),
wherein the transistor is an amplification transistor that constitutes part of a pixel circuit (Figs. 20/21/25/41/42, each pixel of the image sensor, 10 is configured to transfer charges accumulated in a photodiode to a floating diffusion (FD) via an AMP, amplifying transistor, [0125]).
Regarding Claim 3, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
SHIMIZU teaches a solid-state imaging device (Figs. 5/7, MOSFET with a fin structure, [0133]), wherein
the fin (Figs. 5/7, 100/200, vertical transistor is a MOSFET with a fin structure, [0133]) is formed by a groove dug down (Fig. 5, 16a/16b/16c, first/second/third trench, [0026], [0031]) from a main surface (Fig. 5, 36, JFET region [0115]) of the first semiconductor layer (Fig. 5, 10, silicon carbide layer, [0031]) along a thickness direction (annotated Figure 5), and
the electric field relaxation section (Fig. 5, 38a/38b/38c, field relaxation region, [0079]) is provided in a bottom of the groove (Fig. 5, 16a/16b/16c, first/second/third trench, [0026], [0031], [0079]).
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NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the fin (Figs. 28, fin F, [0066]) is formed by a groove dug down (Fig. 28, 103, element isolation trench, [0160]) from a main surface (Fig. 28, MA, memory cell region, [0162]) of the first semiconductor layer (Fig. 28, 100, semiconductor substrate) along a thickness direction (Fig. 28, Z- direction), and
the electric field relaxation section (Figs. 3/30, HK, a high dielectric constant film, [0065-0066], [0164-0165]) is provided in a bottom of the groove (Fig. 28, 103, element isolation trench, [0160]).
Regarding Claim 4, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 3.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) includes an insulator having a higher dielectric constant than silicon oxide (an Al2O3 film, a HfO film, a Ta2O5 film, a SiTiO3 film, a HfSiO film, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]).
Regarding Claim 5, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Fig. 3, HK, a high dielectric constant film, [0065-0066]) includes the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]) and the insulator (Figs. 14/15, ONO insulating film, [0115]) formed on the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]).
Regarding Claim 6, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator (Figs. 14/15, ONO insulating film, [0115]) includes a first insulator (Fig. 15, 107, middle insulating film (includes a silicon nitride film), [0163]) and a second insulator (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) formed on the first insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]), the second insulator (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) having a lower dielectric constant (note: according to Wikipedia, https://www.en.wikipedia.org/wiki/Relative_permitivity, the dielectric constant of silicon dioxide (3.9) is lower than the dielectric constant of silicon nitride (7-8)) than the first insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]).
Regarding Claim 7, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator has a dielectric constant that gradually becomes lower from the bottom of the groove toward an opening of the groove (annotated Figure 16).
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Regarding Claim 8, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) includes a first silicon oxide film (Fig. 15, 106, lower insulating film (includes a silicon nitride film), [0163]) and the insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]) formed on the first silicon oxide film (Fig. 15, 106, lower insulating film (includes a silicon nitride film), [0163]).
Regarding Claim 9, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) further includes a second silicon oxide film (Fig. 15, 108, upper insulating film, (includes a silicon oxide film), [0163]) on the insulator (Fig. 15, 107, middle insulating film, (includes a silicon nitride film), [0163]).
Regarding Claim 10, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator is silicon oxide or aluminum oxynitride (an Al2O3 film, a HfO film, a Ta2O5 film, a SiTiO3 film, a HfSiO film, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]).
TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), wherein
the insulator is silicon oxide or aluminum oxynitride (as the oxide film, in order to further reduce the gate leak, a hafnium oxide film, a zirconium oxide film, or the like may be used; as the oxynitride film, a silicon oxynitride film, a hafnium oxynitride film, a zirconium oxynitride film, or the like may be used, in such a manner, a high dielectric film can be used, [133]).
It should be noted that substituting (silicon oxide or aluminum oxynitride) for (hafnium oxide or hafnium oxynitride) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 11, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is a silicon oxynitride film (Fig. 3, a ZrSiON film, and a HfSiON film can be used as the high dielectric constant film, HK, [106]; 108, upper insulating film, includes a silicon oxynitride film, [0063]) that is nitride (Fig. 3, 107, middle insulating film includes a silicon nitride, [0063]) of the gate insulating film (Fig. 12, 104, gate insulating film, CGI, [0113]).
TAYANAKA teaches a solid-state imaging device (Fig. 41, 10, planar type image sensor), wherein
the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is a silicon oxynitride film (as the oxynitride film, a silicon oxynitride film, a hafnium oxynitride film, a zirconium oxynitride film, or the like may be used, in such a manner, a high dielectric film can be used, [133]) that is nitride of the gate insulating film (Fig. 15A, 132, the insulating film, an oxide or a nitride film is used, [0143]).
Regarding Claim 12, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the insulator of the electric field relaxation section (Figs. 3/15, HK, a high dielectric constant film, [0065-0066]) is formed to be thicker (Figs. 3/15, a thick film is deposited over the top of the fin F and top of the element isolation region, 103, [0102]; Fig. 23, the thick film over the top of the element isolation region, 103 has a thickness, t3; t3>t2, [0144-0145]) than the insulator formed in a region other than the electric field relaxation section (Figs. 3/15, a thin film is deposited over each side surface of the fin F, [0102]; the think film over the side surface of the fin F has a thickness, t2, [0144-0145]).
Regarding Claim 13, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 4.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the gate electrode (Fig. 21, MG, memory gate electrode, [0172]) is formed of metal (metal silicide film, [0172]).
Regarding Claim 14, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the gate electrode (Fig. 21, 105, CG/GE, control gate electrode, [0114]) is formed of polycrystalline silicon (Fig. 21, polysilicon film, 105, CG/GE, [0113]) doped with an impurity that decreases a resistance value (Fig. 19, the metal silicide film, SIL can reduce the diffusion resistance or the control resistance, [0126], [132]), and
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is formed to cause a density of the impurity doped (Figs. 19/20, metal silicide film, SL is provided on the SD region with higher impurity concentration than a metal silicide film, SIL is provided on the gate electrode, GE, [0132]) into the gate electrode (Fig. 21, 105, CG/GE, control gate electrode, [0114]) to be lower than a region other than the electric field relaxation section (Fig. 19, MS/MD, source-drain (SD) region, [0132]).
Regarding Claim 15, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is formed to cause the density of the impurity (Fig. 20 SIL, metal silicide film on the MS/MD region with n+/n- type semiconductor region, 111a/111b/119a/119b, [0068-0069] gradually become lower toward the bottom of inside of the groove (Fig. 20, 103, the element isolation region).
Regarding Claim 16, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is formed by the gate electrode (Fig. 21, 105, CG, control gate electrode, [0114]) not doped with the impurity (Fig. 21, 109, conductive film of the memory gate (MG), [0119]).
Regarding Claim 17, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 14.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is formed in an area up to 20% of a height of the fin (annotated Figure 27).
Regarding Claim 18, TAYANAKA as modified by SHIMIZU and NARUMI teaches the solid-state imaging device according to claim 1.
NARUMI further teaches a solid state imaging device (Figs. 1-3, a semiconductor device, [0059]), wherein
the electric field relaxation section (Figs. 3/15/21, HK, a high dielectric constant film, [0065-0066]) is provided on a side of, of the first main electrode (Fig. 21, 111a/111b, MS, source region, [0124-0132]) and the second main electrode, one used as a drain region (Fig. 21, 119a/119b, MD, source region, [0124-0132]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190371846 A1 – Figure 15
STATEMENT OF RELEVANCE – Planar view illustrating a cross-sectional configuration example of the pixel, 410, wherein a high dielectric constant material film is deposited over an entire inner surface of a through hole provided in a semiconductor substrate, 420.
US 20110042552 A1 – Figure 6, [0044]
STATEMENT OF RELEVANCE – A cross-sectional view of a MOS solid-state imaging device, wherein the Si layer, 33, the amplification transistor, address transistor, reset transistor and other formed to constitute a signal scanning circuit.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
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