DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1, 4, 7-8, 15, 17-20 filed on 6/17/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 3, 5-6, and 9-12 have been considered. New Claim(s) 21-23 have been considered and entered. Claim(s) 2, 13-14, and 16 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-9, filed 04/17/2026, with respect to the rejection(s) of claim(s) 1-3, 7-9, 13, and 16-20 under 35 U.S.C. 102(a)(1), and claim(s) 4-6, 10-12, and 14-15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SOYANO.
Regarding Independent Claim 1. The Applicant argues (see Remarks, page 7) that MATSUYAMA fails to disclose or suggest the amended limitations to Claim 1, now recites, “a power semiconductor module comprising: wherein the connecting means comprises…connecting the first semiconductor component…by a third contact area, and wherein the third connecting element…overlaps…and/or second connecting element.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art, SOYANO teaches the power semiconductor module (Figs. 7, 2, semiconductor device function as power module, [0026]) according to claim 1, comprising wherein the connecting means comprises a third connecting element (Fig. 7, 23b, integral terminal) connecting the first semiconductor component (Fig. 7, 30b, IGBT element) with the second track (Figs. 7, 70, plate) by a third contact area (Figs. 7, 20d, metal foil), and wherein the third connecting element (Fig. 7, 23b, integral terminal) partially overlaps the second contact area and/or second connecting element (Fig. 37, 60, wiring terminal).
Regarding Claim(s) 3-12, 15, and 17-20. The independent Claim(s) 11 and 16, and dependent claims 2, 4-10, 12-15, and 17-20 follow similar arguments as Claim 1. Upon further consideration, new grounds of rejection is made based on the prior art mentioned above.
Claim Rejections - 35 USC § 112 (Withdrawn)
Regarding Claim(s) 4, 7, 15, and 17-20. The Applicant amended (see Remarks, pages 6–7) the claims 4, 7, 15, and 17–20 with necessary details as per the previous Office Action filed on 01/22/2026. Therefore, the 112b rejection for claims 4, 7, 15, and 17-20 are currently withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 7-9, and 17-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiroshi Matsuyama, (hereinafter MATSUYAMA), US 20170256483 A1, (prior art used in the previous Office Action filed on 01/22/2026), in view of Shin Soyano et al, (hereinafter SOYANO), US 20090140414 A1.
Regarding Claim 1, MATSUYAMA teaches in Figures 2-5, a power semiconductor module (Figs. 2-5, 100, semiconductor device) comprising two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) which are electrically connected in parallel (Fig. 3, connected via second conductive section, 11a/11b to conductive layers 11/12),
wherein each of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) comprises a first power contact (Fig. 4, C1/C2, first/fourth collector electrode) and a second power contact (Fig. 4, E1/E2, second/fifth emitter electrode),
wherein the first power contacts (Fig. 4, C1/C2, first/fourth collector electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a first track (Fig. 3, 11, conductive layer),
wherein the second power contacts (Fig. 4, E1/E2, second/fifth emitter electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a second track (Figs. 3/4, 12, conductive layer) by a connecting means (annotated Figure 3),
and wherein the connecting means (annotated Figure 3) comprises at least a first connecting element (Fig. 3, bonding wire, [0043]) connecting a first semiconductor component (Fig. 3, 22, semiconductor chip) of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Fig. 3, 12, conductive layer) via a first contact area (Fig. 3, 12b, connected section),
and a second connecting element (Fig. 3, bonding wire, [0043]) connecting a second semiconductor component (Fig. 3, 22, semiconductor chip) of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) with the second track (Fig. 3, 12, conductive layer) via a second contact area (Fig. 3, 12c, connected section),
wherein the second connecting element (Fig. 3, bonding wire, [0043]) partially overlaps the first contact area (Fig. 3, 12b, connected section) and/or first connecting element (Fig. 3, bonding wire, [0043]).
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MATSUYAMA does not explicitly disclose a power semiconductor module comprising wherein the connecting means comprises a third connecting element connecting the first semiconductor component with the second track by a third contact area, and wherein the third connecting element partially overlaps the second contact area and/or second connecting element.
SOYANO teaches a power semiconductor module (Figs. 7, 2, semiconductor device function as power module, [0026, comprising wherein the connecting means comprises a third connecting element (Fig. 7, 23b, integral terminal) connecting the first semiconductor component (Fig. 7, 30b, IGBT element) with the second track (Figs. 7, 70, plate) by a third contact area (Figs. 7, 20d, metal foil), and
wherein the third connecting element (Fig. 7, 23b, integral terminal) partially overlaps the second contact area and/or second connecting element (Fig. 37, 60, wiring terminal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of SOYANO, such that a power semiconductor module comprising wherein the connecting means comprises a third connecting element connecting the first semiconductor component with the second track by a third contact area, and wherein the third connecting element partially overlaps the second contact area and/or second connecting element, so that to achieve a semiconductor device which is provided with semiconductor elements housed in the resin case and in which the layout of the wiring terminal can be changed easily (SOYANO, [0012]).
Regarding Claim 3, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), comprising at least two connecting elements (Fig. 3, bonding wire, [0043]) per semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip), which connecting elements (Fig. 3, bonding wire, [0043]) connect the semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Figs. 3/4, 12, conductive layer).
Regarding Claim 7, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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Regarding Claim 8, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a landing area of the connecting means (annotated Figure 3) on the second track (Figs. 3, 12, conductive layer) is no larger than 150% of the sum of the contact areas (Fig. 3, 12a+12b+12c+12d, sum of the connected sections) of the connecting means (annotated Figure 3) in contact with the second track (Figs. 3, 12, conductive layer).
Regarding Claim 9, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein the at least two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are switching components (Fig. 3, switching function, [0054]).
Regarding Claim 17, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 3.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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Regarding Claim 18, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 4.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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Regarding Claim 19, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 5.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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Regarding Claim 20, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 6.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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Regarding Claim 21, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 8.
MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a landing area of the connecting means (annotated Figure 3) on the second track (Figs. 3, 12, conductive layer) is no larger than 120% of the sum of the contact areas (Fig. 3, 12a+12b+12c+12d, sum of the connected sections) of the connecting means (annotated Figure 3) in contact with the second track (Figs. 3, 12, conductive layer).
Regarding Claim 22, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 8.
MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein a landing area of the connecting means (annotated Figure 3) on the second track (Figs. 3, 12, conductive layer) is no larger than 110% of the sum of the contact areas (Fig. 3, 12a+12b+12c+12d, sum of the connected sections) of the connecting means (annotated Figure 3) in contact with the second track (Figs. 3, 12, conductive layer).
Regarding Claim 23, MATSUYAMA teaches in Figures 2-5, a power semiconductor module (Figs. 2-5, 100, semiconductor device) comprising two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) which are electrically connected in parallel (Fig. 3, connected via second conductive section, 11a/11b to conductive layers 11/12),
wherein each of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) comprises a first power contact (Fig. 4, C1/C2, first/fourth collector electrode) and a second power contact (Fig. 4, E1/E2, second/fifth emitter electrode),
wherein the first power contacts (Fig. 4, C1/C2, first/fourth collector electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a first track (Fig. 3, 11, conductive layer),
wherein the second power contacts (Fig. 4, E1/E2, second/fifth emitter electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a second track (Figs. 3/4, 12, conductive layer) by a connecting means (annotated Figure 3),
and wherein the connecting means (annotated Figure 3) comprises at least a first connecting element (Fig. 3, bonding wire, [0043]) connecting a first semiconductor component (Fig. 3, 22, semiconductor chip) of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Fig. 3, 12, conductive layer) via a first contact area (Fig. 3, 12b, connected section),
wherein a side of the first semiconductor component (Figs. 2/3, 22, semiconductor chip) facing a landing area (annotated Figure 3) of the first, second and third connecting elements (Fig. 3, bonding wire, [0043]) and a side of and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) facing the landing area (annotated Figure 3) are oriented at an angle between 45 degrees and 135 degrees to each other (annotated Figure 3).
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MATSUYAMA does not explicitly disclose a power semiconductor module comprising wherein the connecting means comprises a second connecting element connecting a second semiconductor component of the two or more semiconductor components with the second track via a second contact area, and wherein the second connecting element partially overlaps the first contact area and/or first connecting element.
SOYANO teaches a power semiconductor module (Figs. 7, 2, semiconductor device function as power module, [0026, comprising wherein the connecting means comprises a second connecting element (Fig. 7, 23a, integral terminal) connecting a second semiconductor component (Fig. 7, 30a, IGBT element) of the two or more semiconductor components (Fig. 3, 30a/30b, IGBT element) with the second track (Figs. 7, 70, plate) via a second contact area (Figs. 7, 20d, metal foil), and
wherein the second connecting element (Fig. 7, 23b, integral terminal) partially overlaps the first contact area and/or first connecting element (Fig. 37, 60, wiring terminal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of SOYANO, such that a power semiconductor module comprising wherein the connecting means comprises a second connecting element connecting a second semiconductor component of the two or more semiconductor components with the second track via a second contact area, and wherein the second connecting element partially overlaps the first contact area and/or first connecting element, so that to achieve a semiconductor device which is provided with semiconductor elements housed in the resin case and in which the layout of the wiring terminal can be changed easily (SOYANO, [0012]).
Claim(s) 4-6, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of SOYANO as applied to claims 1, 3, 7-9, and 17-23 above, and further in view of Lawrence Edward Rinehart et al, (hereinafter RINEHART), US 5926372 A, (prior art used in the previous Office Action filed on 01/22/2026).
Regarding Claim 4, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA as modified by SOYANO does not explicitly disclose the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated from said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator.
RINEHART teaches the power semiconductor module (Fig. 1, 10, power block), wherein the second track (Fig. 2, 12, base plate) comprises a protrusion (annotated Figure 2, 24, corresponding lead frames), wherein a first side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the first semiconductor component (Fig. 2, 22, dies) and separated from said first semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer), and wherein a second side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the second semiconductor component (Fig. 2, 22, dies), and separated from said second semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MATSUYAMA as modified by SOYANO to incorporate the teachings of RINEHART, such that the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated from said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator. The insulating substrate (14) having an insulating layer (16) provides the electrical isolation between the base plate (12), the silicon dies (22) and the lead frames (24) to manufacture high power density modules (RINEHART, [Col. 3, Lines 5-15]; [Col 1, Lines 15-30]).
Regarding Claim 5, MATSUYAMA as modified by SOYANO, and RINEHART teaches the power semiconductor module according to claim 4.
RINEHART further teaches the power semiconductor module (Fig. 1, 10, power block), wherein the protrusion (annotated Figure 2, 24, corresponding lead frames) is V-shaped (annotated Figure 2).
Regarding Claim 6, MATSUYAMA as modified by SOYANO and RINEHART teaches the power semiconductor module according to claim 4.
RINEHART further teaches the power semiconductor module (Fig. 1, 10, power block), wherein a gate signal conductor (Fig. 2, 26, aluminum wire interconnect, [Col. 3, Lines 30-35]) is disposed in the insulating gap (Fig. 1, 16, insulating layer) between the protrusion (annotated Figure 2, 24, corresponding lead frames) and at least one of the first semiconductor component or the second semiconductor component (Fig. 2, 22, dies).
Regarding Claim 15, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 3.
MATSUYAMA as modified by SOYANO does not explicitly disclose the power semiconductor module, wherein the second track comprises a protrusion, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated from said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator.
RINEHART teaches the power semiconductor module (Fig. 1, 10, power block), wherein the second track (Fig. 2, 12, base plate) comprises a protrusion (annotated Figure 2, 24, corresponding lead frames), wherein a first side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the first semiconductor component (Fig. 2, 22, dies) and separated from said first semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer), and wherein a second side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the second semiconductor component (Fig. 2, 22, dies), and separated from said second semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MATSUYAMA as modified by SOYANO to incorporate the teachings of RINEHART, such that the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated from said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator. The insulating substrate (14) having an insulating layer (16) provides the electrical isolation between the base plate (12), the silicon dies (22) and the lead frames (24) to manufacture high power density modules (RINEHART, [Col. 3, Lines 5-15]; [Col 1, Lines 15-30]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of SOYANO as applied to claims 1, 3, 7-9, and 17-23 above, and further in view of Nicola Schulz et al, (hereinafter SCHULZ), US 20120199989 A1, (prior art used in the previous Office Action filed on 01/22/2026).
Regarding Claim 10, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA further teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device), wherein the connecting means (annotated Figure 3 above) comprises one or more ribbon bonds (Fig. 3, bonding wire, [0043]).
Though MATSUYAMA teaches the connecting means comprises bonding wire, MATSUYAMA as modified by SOYANO does not explicitly disclose the power semiconductor module, wherein the connecting means comprises one or more ribbon bonds.
SCHULZ teaches the power semiconductor module (Fig. 1, 10, power circuit arrangement), wherein the connecting means (annotated Figure 1) comprises one or more ribbon bonds (Fig. 1, 25, bonding elements being bonding wires or bonding metal sheet, [0039-0040]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MATSUYAMA as modified by SOYANO to incorporate the teachings of SCHULZ, such that the power semiconductor module, wherein the connecting means comprises one or more ribbon bonds, so that the intermediate contact device being integrally formed with the bonding element saves costs and simplifies the mounting of arrangement (SCHULZ, [0026]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of SOYANO as applied to claims 1, 3, 7-9, and 17-23 above, and further in view of Koichiro Iyama, (hereinafter IYAMA), US 20190157194 A1, (prior art used in the previous Office Action filed on 01/22/2026).
Regarding Claim 11, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA as modified by SOYANO does not explicitly disclose the power semiconductor module in a vehicle.
IYAMA teaches the power semiconductor module (Fig. 16, 100, semiconductor module) in a vehicle (Fig. 16, 300, an electric vehicle).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MATSUYAMA as modified by SOYANO to incorporate the teachings of IYAMA, such that the power semiconductor module in a vehicle enable to suppress a temperature rise (IYAMA, [0101]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of SOYANO as applied to claims 1, 3, 7-9, and 17-23 above, and further in view of Kazuo Aoki et al, (hereinafter AOKI), US 20080290506 A1, (prior art used in the previous Office Action filed on 01/22/2026).
Regarding Claim 12, MATSUYAMA as modified by SOYANO teaches the power semiconductor module according to claim 1.
MATSUYAMA as modified by SOYANO does not explicitly disclose the power semiconductor module in an inverter.
AOKI teaches the power semiconductor module (Fig. 1, 1, semiconductor module) in an inverter (Fig. 6, inverter circuit).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have MATSUYAMA as modified by SOYANO to incorporate the teachings of AOKI, such that a power module in an inverter, so that all switching elements forming the three-phase AC inverter circuit are provided to the base plate integrally, whereby the three-phase AC inverter circuit having a small size and light weight can be easily be formed using the semiconductor module in an inverter that demonstrates a heating value (AOKI, [0003], [0078]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20170317015 A1 – Figure 10
STATEMENT OF RELEVANCE – A schematic perspective view of a power module package is that a conductive unit is configured to interconnect different components, [0059].
US 20160056132 A1 – Figure 21
STATEMENT OF RELEVANCE – A perspective view of a section of a circuit carrier of a semiconductor module having a construction of two or more than two semiconductor chips electrically connected in parallel by virtue of their load terminals being electrically conductively connected to one another, [0097].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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