DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/17/2023 and 11/13/2023 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Preliminary Amendment
The preliminary amendment with respect to the claims, abstract and specification filed on 10/17/2023 have been fully considered for examination.
Response to Arguments
Applicant’s amendments (see Remarks, page 10) with respect to the substitute specification and marked-up versions filed on 10/17/2023 are considered and entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4, 7, and 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 4, and 14-15 have the following limitation: “a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator.” These claims are unclear and indefinite, since the paragraph [0036] of the instant application recites, “a first side of the protrusion is located next to a side of the first semiconductor component and separated from said first semiconductor component by an insulating gap or an insulator.”
Claim(s) 7, 16-17, and 19-20 have the following limitation: “at least the first semiconductor component and the second semiconductor component are oriented at an angle between 45 degrees and 135 degrees to each other.” These claims are indefinite because “oriented at an angle…to each other” has no generally accepted definition for a given power module and the Specification does not clearly disclose or suggest the claim limitation mentioned above, other than a close relevant statement, “the angle is measured between...facing the protrusion…second track” is given in the paragraph [0043] of the instant application.
Claim(s) 5-6, and 18 depend on rejected claim 4 are also rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiroshi Matsuyama, (hereinafter MATSUYAMA), US 20170256483 A1.
Regarding Claim 1, MATSUYAMA teaches in Figures 2-5, a power semiconductor module (Figs. 2-5, 100, semiconductor device) comprising two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) which are electrically connected in parallel (Fig. 3, connected via second conductive section, 11a/11b to conductive layers 11/12),
wherein each of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) comprises a first power contact (Fig. 4, C1/C2, first/fourth collector electrode) and a second power contact (Fig. 4, E1/E2, second/fifth emitter electrode),
wherein the first power contacts (Fig. 4, C1/C2, first/fourth collector electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a first track (Fig. 3, 11, conductive layer),
wherein the second power contacts (Fig. 4, E1/E2, second/fifth emitter electrode) of each semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are electrically connected to a second track (Figs. 3/4, 12, conductive layer) by a connecting means (annotated Figure 3),
and wherein the connecting means (annotated Figure 3) comprises at least a first connecting element (Fig. 3, bonding wire, [0043]) connecting a first semiconductor component (Fig. 3, 22, semiconductor chip) of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Fig. 3, 12, conductive layer) via a first contact area (Fig. 3, 12b, connected section),
and a second connecting element (Fig. 3, bonding wire, [0043]) connecting a second semiconductor component (Fig. 3, 22, semiconductor chip) of the two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) with the second track (Fig. 3, 12, conductive layer) via a second contact area (Fig. 3, 12c, connected section),
wherein the second connecting element (Fig. 3, bonding wire, [0043]) partially overlaps the first contact area (Fig. 3, 12b, connected section) and/or first connecting element (Fig. 3, bonding wire, [0043]).
Regarding Claim 2, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, comprising a third connecting element (Fig. 3, bonding wire, [0043]) connecting the first semiconductor component (Fig. 3, 22, semiconductor chip) with the second track (Figs. 3/4, 12, conductive layer) by a third contact area (Fig. 3, 12a, connected section),
wherein the third connecting element (Fig. 3, bonding wire, [0043]) partially overlaps the first or second contact area (Fig. 3, 12b/12c, connected section) and/or first or second connecting element (Fig. 3, bonding wire, [0043]).
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Regarding Claim 3, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, comprising at least two connecting elements (Fig. 3, bonding wire, [0043]) per semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip), which connecting elements (Fig. 3, bonding wire, [0043]) connect the semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Figs. 3/4, 12, conductive layer).
Regarding Claim 7, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Regarding Claim 8, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, wherein a landing area of the connecting means (annotated Figure 3) on the second track (Figs. 3, 12, conductive layer) is no larger than 150%, preferably 120%, and most preferably 110% of the sum of the contact areas (Fig. 3, 12a+12b+12c+12d, sum of the connected sections) of the connecting means (annotated Figure 3) in contact with the second track (Figs. 3, 12, conductive layer).
Regarding Claim 9, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, wherein the at least two or more semiconductor components (Fig. 3, 21/22/23/24/25/26, semiconductor chip) are switching components (Fig. 3, switching function, [0054]).
Regarding Claim 13, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 2, comprising at least two connecting elements (Fig. 3, bonding wire, [0043]) per semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip), which connecting elements (Fig. 3, bonding wire, [0043]) connect the semiconductor component (Fig. 3, 21/22/23/24/25/26, semiconductor chip) to the second track (Figs. 3, 12, conductive layer).
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Regarding Claim 16, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 2, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Regarding Claim 17, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 3, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Regarding Claim 18, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 4, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Regarding Claim 19, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 5, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Regarding Claim 20, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 6, wherein at least the first semiconductor component (Figs. 2/3, 22, semiconductor chip) and the second semiconductor component (Figs. 2/3, 23, semiconductor chip) are oriented at an angle between 45 degrees and 135 degrees to each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of Lawrence Edward Rinehart et al, (hereinafter RINEHART), US 5926372 A.
Regarding Claim 4, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1.
MATSUYAMA does not explicitly disclose the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator.
RINEHART teaches the power semiconductor module (Fig. 1, 10, power block), wherein the second track (Fig. 2, 12, base plate) comprises a protrusion (annotated Figure 2, 24, corresponding lead frames), wherein a first side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the first semiconductor component (Fig. 2, 22, dies) and separated by said first semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer), and wherein a second side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the second semiconductor component (Fig. 2, 22, dies), and separated from said second semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of RINEHART, such that the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator. The insulating substrate (14) having an insulating layer (16) provides the electrical isolation between the base plate (12), the silicon dies (22) and the lead frames (24) to manufacture high power density modules (RINEHART, [Col. 3, Lines 5-15]; [Col 1, Lines 15-30]).
Regarding Claim 5, MATSUYAMA as modified by RINEHART teaches the power semiconductor module according to claim 4.
RINEHART further teaches the power semiconductor module (Fig. 1, 10, power block), wherein the protrusion (annotated Figure 2, 24, corresponding lead frames) is V-shaped (annotated Figure 2).
Regarding Claim 6, MATSUYAMA as modified by RINEHART teaches the power semiconductor module according to claim 4.
RINEHART further teaches the power semiconductor module (Fig. 1, 10, power block), wherein a gate signal conductor (Fig. 2, 26, aluminum wire interconnect, [Col. 3, Lines 30-35]) is disposed in the insulating gap (Fig. 1, 16, insulating layer) between the protrusion (annotated Figure 2, 24, corresponding lead frames) and at least one of the first semiconductor component or the second semiconductor component (Fig. 2, 22, dies).
Regarding Claim 14, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 2.
MATSUYAMA does not explicitly disclose the power semiconductor module, wherein the second track comprises a protrusion, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator.
RINEHART teaches the power semiconductor module (Fig. 1, 10, power block), wherein the second track (Fig. 2, 12, base plate) comprises a protrusion (annotated Figure 2, 24, corresponding lead frames), wherein a first side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the first semiconductor component (Fig. 2, 22, dies) and separated by said first semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer), and wherein a second side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the second semiconductor component (Fig. 2, 22, dies), and separated from said second semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of RINEHART, such that the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator. The insulating substrate (14) having an insulating layer (16) provides the electrical isolation between the base plate (12), the silicon dies (22) and the lead frames (24) to manufacture high power density modules (RINEHART, [Col. 3, Lines 5-15]; [Col 1, Lines 15-30]).
Regarding Claim 15, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 3.
MATSUYAMA does not explicitly disclose the power semiconductor module, wherein the second track comprises a protrusion, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator.
RINEHART teaches the power semiconductor module (Fig. 1, 10, power block), wherein the second track (Fig. 2, 12, base plate) comprises a protrusion (annotated Figure 2, 24, corresponding lead frames), wherein a first side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the first semiconductor component (Fig. 2, 22, dies) and separated by said first semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer), and wherein a second side of the protrusion (annotated Figure 2, 24, corresponding lead frames) is located next to a side of the second semiconductor component (Fig. 2, 22, dies), and separated from said second semiconductor component (Fig. 2, 22, dies) by an insulating gap or an insulator (Fig. 1, 16, insulating layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of RINEHART, such that the power semiconductor module, wherein the second track comprises a protrusion, wherein a first side of the protrusion is located next to a side of the first semiconductor component and separated by said first semiconductor component by an insulating gap or an insulator, and wherein a second side of the protrusion is located next to a side of the second semiconductor component, and separated from said second semiconductor component by an insulating gap or an insulator. The insulating substrate (14) having an insulating layer (16) provides the electrical isolation between the base plate (12), the silicon dies (22) and the lead frames (24) to manufacture high power density modules (RINEHART, [Col. 3, Lines 5-15]; [Col 1, Lines 15-30]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of Nicola Schulz et al, (hereinafter SCHULZ), US 20120199989 A1.
Regarding Claim 10, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1, wherein the connecting means (annotated Figure 3) comprises one or more ribbon bonds (Fig. 3, bonding wire, [0043]).
Though MATSUYAMA teaches the connecting means comprises bonding wire, MATSUYAMA does not explicitly disclose the power semiconductor module, wherein the connecting means comprises one or more ribbon bonds.
SCHULZ teaches the power semiconductor module (Fig. 1, 10, power circuit arrangement), wherein the connecting means (annotated Figure 1) comprises one or more ribbon bonds (Fig. 1, 25, bonding elements being bonding wires or bonding metal sheet, [0039-0040]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of SCHULZ, such that the power semiconductor module, wherein the connecting means comprises one or more ribbon bonds, so that the intermediate contact device being integrally formed with the bonding element saves costs and simplifies the mounting of arrangement (SCHULZ, [0026]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of Koichiro Iyama, (hereinafter IYAMA), US 20190157194 A1.
Regarding Claim 11, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1.
MATSUYAMA does not explicitly disclose the power semiconductor module in a vehicle.
IYAMA teaches the power semiconductor module (Fig. 16, 100, semiconductor module) in a vehicle (Fig. 16, 300, an electric vehicle).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of IYAMA, such that the power semiconductor module in a vehicle enable to suppress a temperature rise (IYAMA, [0101]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUYAMA, in view of Kazuo Aoki et al, (hereinafter AOKI), US 20080290506 A1.
Regarding Claim 12, MATSUYAMA teaches in Figures 2-5, the power semiconductor module (Figs. 2-5, 100, semiconductor device) according to claim 1.
MATSUYAMA does not explicitly disclose the power semiconductor module in an inverter.
AOKI teaches the power semiconductor module (Fig. 1, 1, semiconductor module) in an inverter (Fig. 6, inverter circuit).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified MATSUYAMA to incorporate the teachings of IYAMA, such that all switching elements forming the three-phase AC inverter circuit are provided to the base plate integrally, whereby the three-phase AC inverter circuit having a small size and light weight can be easily be formed using the semiconductor module in an inverter that demonstrates a heating value (AOKI, [0003], [0078]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160056132 A1 – Figure 29
STATEMENT OF RELEVANCE – Plan view of a section of a circuit arrangement comprising a plurality of semiconductor chips arranged in series. The connection conductors connecting the semiconductor chip with the collecting conductor track.
US 20180102309 A1 – Figures 1A-1D
STATEMENT OF RELEVANCE – Power semiconductor module includes a base plate, a substrate, a lead frame and a plurality of semiconductor elements that are electrically connected together.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812