DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on May 26th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on May 26th, 2026 is acknowledged and isanswered as follows.
Applicant's remarks, see pg. 6, with respect to the objections of claims under formalities have been considered and are persuasive. Therefore, the objections of the claims have been withdrawn.
Applicant's arguments, see pgs. 6-9, with respect to the rejections of claims under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection (same prior art, but different interpretation).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-7 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOSHIOKA et al. (Pub. No.: US 2011/0204380 A1), hereinafter as YOSHIOKA.
Regarding claim 1, YOSHIOKA discloses a semiconductor device in Figs. 1-4 comprising: a channel layer (layer 3) on a substrate (substrate 1) (see Fig. 2 and [0027]); a barrier layer (combination of layer 4 and vertical portions of insulating film 6 in trench portion 8) on the channel layer (see Fig. 2 and [0027]); and a gate electrode (gate electrode 33), a source electrode (source electrode 31), and a drain electrode (drain electrode 33) on the substrate via the channel layer and the barrier layer and that extend in a first direction (vertical direction in Fig. 1), wherein the channel layer or the barrier layer has a plurality of non-conductive regions (plurality of vertical portions insulating layer 6 in trench portions 8) at positions opposed to the gate electrode and arranged side by side, with a determined interval (interval equal to width W2) interposed therebetween the plurality of non-conductive regions (between at least 2 portions of insulating layer 6 in one trench portion 8), in an extending direction of the gate electrode (extending direction of gate electrode 33), and the plurality of non-conductive regions is configured to inhibit a current from flowing to the channel layer (portions of insulating layer 6 in trench portions 8 blocking current from gate electrode 33 flowing to layer 3) (see Figs. 2-4 and [0028-0029]).
Regarding claim 5, YOSHIOKA discloses the semiconductor device according to claim 1, wherein the barrier layer has a non-conductive region of the plurality of non-conductive regions (layer 4 has trench portion 8 within), and the barrier layer has, as the non-conductive region, an opening (trench portion 8) that penetrates the barrier layer (see Figs. 2 and 4).
Regarding claim 6, YOSHIOKA discloses the semiconductor device according to claim 5, wherein the gate electrode has a branch section (a portion of gate electrode 33 within recess regions 42) that penetrates the channel layer through the opening (penetrate into portions of layer 3) (see Figs. 1, 2, 4 and [0024]).
Regarding claim 7, YOSHIOKA discloses the semiconductor device according to claim 6, wherein the branch section includes a material having a thermal conductivity (thermal conductivity of metal Ni/Au of gate electrode 33) higher than a thermal conductivity of the channel layer (higher than thermal conductivity of GaN of layer 3) (see [0030]).
Regarding claim 14, YOSHIOKA discloses the semiconductor device according to claim 6, wherein the branch section is isolated from the substrate via a gate insulating film (horizonal portions of insulating layer 6 in within recess regions 42/trench portions 8) (see Fig. 1 and 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over MIURA et al. (Pub. No.: US 2015/0221758 A1), hereinafter as MIURA and in view of YOSHIOKA et al. (Pub. No.: US 2011/0204380 A1), hereinafter as YOSHIOKA
Regarding claim 11, MIURA discloses a semiconductor device in Figs. 5-6 comprising: a channel layer (layer CH) on a substrate (substrate S); and a barrier layer (layer BA) on the channel layer (see Fig. 5 and [0084-0085]); and a plurality of gate electrodes (plurality of gate GE), a plurality of source electrodes (plurality of source electrodes SE), and a plurality of drain electrodes (plurality of drain electrodes DE) on the substrate via the channel layer and the barrier layer and extend in a first direction (Y direction), wherein the plurality of source electrodes and the plurality of drain electrodes are alternately arranged in a second direction (x-direction) intersecting the first direction, the plurality of gate electrodes is arranged one by one between a respective one of the plurality of source electrodes and a respective one of the plurality of drain electrode, and the channel layer or the barrier layer (see Figs. 5-6 and [0086-0090]).
MIURA fails to disclose one of the channel layer or the barrier layer has a plurality of non-conductive regions at positions opposed to the respective gate electrodes of the plurality of gate electrodes and arranged side by side, with a predetermined interval interposed therebetween, in an extending direction of the plurality of gate electrodes, the plurality of non-conductive regions is configured to inhibit a current from flowing to the channel layer.
YOSHIOKA discloses a semiconductor device in Figs. 1-4 comprising: a channel layer (layer 3) on a substrate (substrate 1) (see Fig. 2 and [0027]); a barrier layer (combination of layer 4 and vertical portions of insulating film 6 in trench portion 8) on the channel layer (see Fig. 2 and [0027]); and a gate electrode (gate electrode 33), a source electrode (source electrode 31), and a drain electrode (drain electrode 33) on the substrate via the channel layer and the barrier layer and that extend in a first direction (vertical direction in Fig. 1), wherein the channel layer or the barrier layer has a plurality of non-conductive regions (plurality of portions insulating layer 6 in trench portions 8) at positions opposed to the gate electrode and arranged side by side, with a determined interval (interval equal to width W2) interposed therebetween the plurality of non-conductive regions (between at least 2 portions of insulating layer 6 in one trench portion 8), in an extending direction of the gate electrode (extending direction of gate electrode 33), and the plurality of non-conductive regions is configured to inhibit a current from flowing to the channel layer (portions of insulating layer 6 in trench portions 8 blocking current from gate electrode 33 flowing to layer 3) (see Figs. 2-4 and [0028-0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the plurality of non-conductive regions (portions of insulating layer 6 in the plurality of trench portion 8) of YOSHIOKA into the semiconductor device of MIURA for the channel layer and the barrier layer having the plurality of non-conductive regions forming at positions opposed to the plurality of gate electrodes and arranged side by side for inhibiting a current from flowing into the channel layer because the modified structure would increase mobility within the channel layer of the transistor and further reduce ON resistance of the transistor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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