DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “SINGLE-TRANSISTOR STRUCTURE, MULTI-TRANSISTOR STRUCTURE, AND ELECTRONIC APPARATUS, EACH COMPRISING A CHANNEL ELECTRODE”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 10, 13, 18-19, 26, and 29-33 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Dai, Ming-zhi (CN 108767015; hereinafter Dai).
Regarding claim 1, Dai discloses single-transistor structure, comprising:
a substrate (10; Figs 3,4; ¶ [0058]);
a channel (not labeled, between 11 and 12; Figs 3,4; ¶ [0058]), a source (11; Figs 3,4; ¶ [0058]) and a drain (12; Figs 3,4; ¶ [0058]), which are located at a same side of the substrate, wherein: the channel extends along an extension direction (horizontal direction; Figs 3,4), and has a first end (the end nearest source 11; Fig 11) and a second end (the end nearest the drain 12; Fig 11), which are opposite to each other, along the extension direction, the source is in electrical contact with the first end, and the drain is in electrical contact with the second end;
a gate (15; Fig 3; ¶ [0063]) disposed between the source and the drain, wherein the gate covers a part of the channel, and an insulating layer (20; Fig 3; ¶ [0058]) is sandwiched between the channel and the gate; and
a channel electrode (output terminal 17; Figs 3,4; ¶ [0058]), wherein the channel electrode is in electrical contact with another part of the channel which is exposed from the gate, the channel electrode and the part of the channel covered by the gate overlap partially along the extension direction, and the channel electrode is isolated and insulated from the gate (as shown by Figs 3,4 and associated description).
Regarding claim 10, Dai discloses single-transistor structure according to claim 1, wherein:
the single-transistor structure serves as a preset electronic component, which is at least one of a logic gate device (¶ [0036], Claim 10), a memory, an optical device, an electrical device, an electronic device, an optoelectronic device, a photonic device, an electronic device, an optoelectronic device, or a bionic/neuromorphic device;
the gate (15; Fig 3) serves as an input electrode (¶ [0058]) of the preset electronic component; and the channel electrode (17; Figs 3,4) serves as at least one of an output electrode of the preset electronic component (¶ [0058]) or another input electrode of the preset electronic component.
Regarding claim 13, Dai discloses single-transistor structure according to claim 1, wherein along the extension direction, a length L1 of the channel is greater than a length L2 of the channel electrode, and the channel electrode is disposed between the first end and the second end and does not directly contact the source or the drain (as can be observed in Fig 13, and associated description).
Regarding claim 18, Dai discloses single-transistor structure according to claim 1, wherein a length of the gate (15; Fig 3) is greater than or equal to a length of the channel, along the extension direction of the channel (as shown in Fig 3, a length of the channel between 11 and 12 is less than a length of the gate 15).
Regarding claim 19, Dai discloses single-transistor structure according to claim 1, wherein the channel electrode (17; Figs 3,4) comprises one (17; Figs 3,4) or more channel sub-electrodes (in the same manner as channel electrode 15 of Figs 2,3 {¶ [0084]} of the instant application).
Regarding claim 26, Dai discloses an electronic apparatus, which is a circuit (¶ [0040-41]) or a transistor array, comprising: the single-transistor structure according to claim 1.
Regarding claim 29, Dai discloses the single-transistor structure according to claim 1, wherein the channel electrode (output terminal 17) is made of an optical material, an electrical material, an electronic material (¶ [0064]), an optoelectronic material, or a photonic material.
Regarding claim 30, Dai discloses the single-transistor structure according to claim 1, wherein the gate (15; Fig 3) covers the part of the channel (not labeled, between 11 and 12; Fig 3; as applied to claim 1 and shown in Fig 3).
Regarding claim 31, Dai discloses the single-transistor structure according to claim 1, wherein the channel electrode is the material which could form a junction with the channel or which could extract a fixed voltage from the channel (as applied to claim 1, in order for the output terminal to provide an output, as intended; (¶ [0064]).
Regarding claim 32, Dai discloses the single-transistor structure according to claim 1, wherein the channel electrode could be formed via doping (doped semiconductor material; ¶ [0064]).
Regarding claim 33, Dai discloses the single-transistor structure according to claim 1, wherein the channel electrode is the material which could form a junction with the channel (may be formed simultaneously with the source and drain {which form a junction with the channel in order for the transistor to function as intended}; ¶ [0064]) or which could extract a fixed voltage from the channel, and the channel electrode could be formed via doping (doped semiconductor material; ¶ [0064]).
Claims 1-7, and 17 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Yang; Kuo-Nan et al. (US 2006/0084211; hereinafter Yang).
Regarding claim 1, Yang discloses single-transistor structure (entire document, in particular Figs 2,7-10; ¶ [0015-21]), comprising:
a substrate (40; Fig 8; ¶ [0015]);
a channel (fin region 50, Fig 7; the portion, labeled 44, beneath gate 54 in Fig 8; ¶ [0016]), a source (46; Fig 7; ¶ [0016]) and a drain (48; Fig 7; ¶ [0016]), which are located at a same side of the substrate, wherein: the channel extends along an extension direction (horizontal direction, as shown in Fig 7), and has a first end (the end nearest source 46; Fig 7) and a second end (the end nearest the drain 48; Fig 7), which are opposite to each other, along the extension direction, the source is in electrical contact with the first end, and the drain is in electrical contact with the second end;
a gate (54; Figs 7-8; ¶ [0017-18]) disposed between the source and the drain, wherein the gate covers a part of the channel, and an insulating layer (52; Fig 8; ¶ [0017]) is sandwiched between the channel and the gate; and
a channel electrode (44; Figs 7-8; ¶ [0018]), wherein the channel electrode is in electrical contact with another part of the channel which is exposed from the gate, the channel electrode and the part of the channel covered by the gate overlap partially along the extension direction, and the channel electrode is isolated and insulated from the gate (as shown by Figs 7,8 and associated description; 44 is in contact with a side of the fin region closer to the label B {Fig 7} and opposite the gate 54/label G {Fig 7}).
Regarding claim 2, Yang discloses single-transistor structure according to claim 1, wherein the channel has a plurality of side surfaces (top, bottom, gate side {label G; Fig 7}, body side {label B; Fig 7} of the fin), wherein at least one side surface of the plurality of side surfaces is partially or totally exposed from the gate for arranging the channel electrode (body side).
Regarding claim 3, Yang discloses single-transistor structure according to claim 2, wherein:
the plurality of side surfaces comprises a first side surface (Yang; top of fin) and a third side surface (bottom) which are opposite to each other, and a second side surface (gate side G) and a fourth side surface (body side B) which are opposite to each other;
the gate comprises at least one of a first sub-gate (the portion on top of the fin {on top of 44, Fig 8; on top of 50, Fig 7}, a second sub-gate (the portion on the gate side G sidewall of fin, on the vertical sidewall of 44 in Fig 8), a third sub-gate or a fourth sub-gate; and the first sub-gate covers at least a portion of the first side surface (as explained; Figs 7,8), the second sub-gate covers at least a portion of the second side surface (as explained; Figs 7,8), the third sub-gate covers at least a portion of the third side surface, and the fourth sub-gate at least covers a portion of the fourth side surface.
Regarding claim 4, Yang discloses single-transistor structure according to claim 2, wherein two adjacent side surfaces (top and gate side G) of the plurality of side surfaces are both covered by corresponding sub-gates, and the corresponding sub-gates are integrated as a whole or separated from each other (integrated as shown in Fig 8).
Regarding claim 5, Yang discloses single-transistor structure according to claim 3, wherein a sub-gate located on one of the plurality of side surfaces (gate side G) is an integral structure or comprises a plurality of electrode blocks (integral with the top side sub-gate and with the portion of 54 extending to the region labeled G; Figs 7,8).
Regarding claim 6, Yang discloses single-transistor structure according to claim 1, wherein the channel electrode serves as at least one of an output electrode or an input electrode (¶ [0021-22]).
Regarding claim 7, Yang discloses single-transistor structure according to claim 3, wherein along a direction pointing from the first side surface to the third side surface, a thickness H1 of the channel is greater than or equal to a thickness H2 of the channel electrode, and the channel electrode is disposed between the first side surface and the third side surface (as shown in Fig 8, a thickness of the fin/channel 44 is equal to the thickness of the channel electrode 44 away from the fin {not beneath 54; Fig 8}, and the channel electrode is disposed between the top and bottom surface of the fin/channel).
Regarding claim 17, Yang discloses single-transistor structure according to claim 1, wherein: a width of the channel is uniform or non-uniform along the extension direction (as shown in Fig 7, a width of the channel 50 is uniform in the horizontal direction between S and D); or a width of the channel electrode is uniform or non-uniform along a direction pointing from an end of the channel electrode connected to the channel to an end of the channel electrode away from the channel.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai), in view of Yang; Kuo-Nan et al. (US 2006/0084211; hereinafter Yang).
Regarding claim 2, Dai discloses single-transistor structure according to claim 1, but in the same embodiment does not disclose wherein the channel has a plurality of side surfaces, wherein at least one side surface of the plurality of side surfaces is partially or totally exposed from the gate for arranging the channel electrode.
In the same field of endeavor, Yang discloses a similar single-transistor structure (entire document, in particular Figs 2,7-10; ¶ [0015-21]) comprising a fin-based channel (fin region 50, Fig 7; the portion, labeled 44, beneath gate 54 in Fig 8; ¶ [0016]) wherein the channel has a plurality of side surfaces (top, bottom, gate side {label G; Fig 7}, body side {label B; Fig 7} of the fin), wherein at least one side surface (top, body side) of the plurality of side surfaces is partially or totally exposed from the gate for arranging a channel electrode (for example, 44; Figs 7-8; ¶ [0018]) arranged at the body side B.)
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the fin-based channel and gate structure of Yang with the single-transistor structure of Dai according to claim 1. One may have been motivated to do this as an alternate structure comprising a fin structure as taught by Yang in order to accommodate design, performance and/or manufacturing requirements for a particular application, and would have had a reasonable expectation of success because of the similar structures and endeavors of Dai and Yang.
Regarding claim 3, Dai in view of Yang discloses single-transistor structure according to claim 2, wherein: the plurality of side surfaces comprises a first side surface (Yang; top side of the fin/channel; Figs 7,8) and a third side surface (Yang; bottom side of the fin) which are opposite to each other, and a second side surface (Yang; gate side {label G; Fig 7} of the fin) and a fourth side surface (Yang; body side {label B; Fig 7}of the fin) which are opposite to each other.
the gate comprises at least one of a first sub-gate (Yang; the portion on top of the fin {on top of 44, Fig 8; on top of 50, Fig 7}, a second sub-gate (Yang; the portion on the gate side G sidewall of fin, on the vertical sidewall of 44 in Fig 8), a third sub-gate or a fourth sub-gate; and the first sub-gate covers at least a portion of the first side surface (Yang; as explained; Figs 7,8), the second sub-gate covers at least a portion of the second side surface (Yang; as explained; Figs 7,8), the third sub-gate covers at least a portion of the third side surface, and the fourth sub-gate at least covers a portion of the fourth side surface.
Regarding claim 9, Dai in view of Yang discloses single-transistor structure according to claim 3, wherein:
the first side surface (top of fin/channel) faces away from the substrate, and the third side surface (bottom) faces the substrate;
at least a part of the third side surface is exposed from the third sub-gate (the third surface is absent a third-sub-gate (both Dai and Yang), and a third sub-gate is not required by claim 3, which requires only one sub-gate); and
the channel electrode is disposed in the substrate and in contact with the part of the third side surface (Dai; 17; Figs 3,4; in view of Yang having the fin/gate structure and Dai having the channel electrode in the substrate, it would have been obvious to arrive at the further limitation of claim 9. One may have been motivated to do so as one of various alternate channel electrode configurations in order to accommodate design, performance and/or manufacturing requirements for a particular application, and would have had a reasonable expectation of success because of the similar structures and endeavors of Dai and Yang.)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai), in view of Kim; Ji-Young et al. (US 2012/0299090; hereinafter Kim).
Regarding claim 11, Dai discloses the single-transistor structure according to claim 10, but does not disclose wherein the gate comprises a plurality of separated sub-gates, which serves as a plurality of input electrodes of the preset electronic component; and/or the channel electrode comprise a plurality of separated channel sub-electrodes, which serves as: a plurality of output electrodes of the preset electronic component, a plurality of input electrodes of the preset electronic component, or at least one input electrode of the preset electronic component and at least one output electrode of the preset electronic component.
In the same field of endeavor, Kim discloses a single-transistor structure (Fig 2; ¶ [0076-81]), wherein a gate (G; Fig 2; ¶ [0078]) comprises a plurality of separated sub-gates (SG1,SG2; Fig 2; ¶ [0078]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the gate of Dai may comprise a plurality of separated sub-gates, which serves as a plurality of input electrodes of the preset electronic component (logic gate device, as applied to claim 10) (Kim; ¶ [0074]; Table 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai), in view of Dai, Ming-zhi (CN 208444843; hereinafter Dai4843).
Regarding claim 12, Dai discloses the single-transistor structure according to claim 1, but does not disclose wherein: the single-transistor structure serves as a memory unit of a memory, the channel electrode and the channel form a junction capacitor to store charges, and the gate and the channel electrode serve as an input control electrode of the memory unit.
In the same field of endeavor, Dai4843 discloses a similar single-transistor structure (¶ [0051-61]) serves as a memory unit of a memory (¶ [0033,0036]), wherein a channel electrode (18; Fig 2,3; ¶ [0052]) and a channel (17; Fig 2,3; ¶ [0051]) form a junction capacitor to store charges (¶ [0052]), and a gate (17; Fig 2,3; ¶ [0051]) and the channel electrode serve as an input control electrode of the memory unit (as is necessary for the described memory to function).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the disclosures of Dai and Dai 4843 to arrive at the further limitations of claim 12. One would have been motivated to do this in order to form the memory unit as disclosed by Dai4843 having the reduced area (Dai4843; ¶ [0060]). One would have had a reasonable expectation of success due to the similarity in the structures and endeavors of the two disclosures.
Claims 15-16, 20-21, 24, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai).
Regarding claim 15, Dai discloses the single-transistor structure according to claim 13, wherein: the single-transistor structure serves as a logic gate device (¶ [0036], Claim 10), and L2<L1/2 (as depicted in in Figs 3,4).
Dai does not disclose the channel electrode (output terminal/electrode 17; Figs 3,4) is closer to the drain than to the source. However, Dai discloses that the location of the channel electrode relative to the drain and source may be adjusted as needed for circuit functionality ¶ [0069]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the channel electrode may be closer to the drain that to the source, as needed for circuit functionality as disclosed by Dai.
Regarding claim 16, Dai discloses the single-transistor structure according to claim 13, but does not disclose wherein: (1) the single-transistor structure serves as a memory unit of a memory, (2) L2> L1/2, and (3) a distance from the channel electrode to the first end is equal to a distance from the channel electrode to the second end.
However, regarding (3), Dai discloses that the location of the channel electrode relative to the drain and source may be adjusted as needed for circuit functionality ¶ [0069]). Accordingly, it would have been obvious to a person having ordinary skill in the art that a distance from the channel electrode to the first end may be equal to a distance from the channel electrode to the second end, as needed for circuit functionality as disclosed by Dai. Further, (2) would have been obvious for similar reason, as such dimensional considerations are routine in the art in order to accommodate a variety of design, performance, and/or manufacturing requirements for a particular application. Regarding (3), there is no particular reason why the single-transistor structure may not be used as a memory unit of a memory, as would have been obvious to a person having ordinary skill in the art, since single-transistor memory cells (units) are well-known in the art.
Regarding claim 20, Dai discloses single-transistor structure according to claim 19, but does not disclose wherein the channel electrode has a plurality of channel sub-electrodes, and the channel sub-electrodes are disposed on a same side surface of the channel or on different side surfaces of the channel. However, it would have been obvious to a person having ordinary skill in the art that this may be the case. One may have been motivated to configure the channel electrode in this manner in order to accommodate a variety of design, performance, and/or manufacturing requirements for a particular application, for example to direct an output signal toward a plurality of signal paths. One would have had a reasonable expectation of success because such considerations and their implementations are well-known in the art.
Regarding claim 21, Dai discloses the single-transistor structure according to claim 21, but does not disclose a multi-transistor structure, comprising a plurality of single-transistor structures, each of which is the single transistor structure according to claim 1. However, it would have been obvious to a person having ordinary skill in the art to have selected a plurality of single-transistor structures according to claim 1 in order to create any number or circuits and/or devices known in the art, and to have combined them into any number of forms of multi-transistor structures, because it is known in the art that circuits and devices may be formed using the function of a transistor in many forms (for example, planar MOSFET, FinFET, nano-sheet, and others). One would have been motivated to do this, in order to reduce an area used by the single-transistor structure as compared to other single-transistor structures known at the time (Dai; ¶ [0042]), and would have had a reasonable expectation of success because the single-transistor structure of claim 1 may be formed using methods similar to other known methods.
Regarding claim 24, Dai discloses the multi-transistor structure according to claim 21, wherein at least two single-transistor structures of the plurality of single-transistor structures have separate sources, separate drains, and separate gates (this is just two single-transistor structures according to claim 1, as applied to claim 21).
Dai does not disclose the at least two single-transistor structures share the channel electrode. However, it would have been obvious to a person having ordinary skill in the art to arrive at the structure with a shared channel electrode. One may have been motivated to do this in order to send or retrieve a same signal or potential to the channel electrode of at least two transistors, as may be required for any number for circuits, and potentially to save an area occupied by the at least two single-transistor structures by sharing the channel electrode. One would have had a reasonable expectation of success because such structural considerations are well-known in the art.
Regarding claim 27, Dai discloses an electronic apparatus, which is a circuit (¶ [0040-41]) or a transistor array, comprising: the single-transistor structure according to claim 21 (as applied to claim 21).
Regarding claim 28, Dai discloses single-transistor structure according to claim 1, but does not disclose wherein the channel electrode has a plurality of channel sub-electrodes, and the channel sub-electrodes are disposed on a same side surface of the channel. However, it would have been obvious to a person having ordinary skill in the art that this may be the case. One may have been motivated to configure the channel electrode in this manner in order to accommodate a variety of design, performance, and/or manufacturing requirements for a particular application, for example to direct an output signal toward a plurality of signal paths. One would have had a reasonable expectation of success because such considerations and their implementations are well-known in the art.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai) in view of Hisamoto; Digh (US 2018/0082745; hereinafter Hisamoto).
Regarding claim 22, Dai discloses the multi-transistor structure according to claim 21, wherein at least two single-transistor structures of the plurality of single-transistor structures have separate sources, separate channels, separate gates and separate channel electrodes (this is just two single-transistor structures according to claim 1, as applied to claim 21).
Dai does not disclose the at least two single-transistor structures share the drain.
In the same field of endeavor, Hisamoto discloses a semiconductor device comprising nonvolatile memory cells using a multi-transistor structure (Fig 2; ¶ [0122-131]) comprising two single-transistor structures (MC(10),MC(00); Figs 1,2; ¶ [0129]) having have separate sources, separate channels, and separate gates (Figs 1,2; ¶ [0128-129]); and the two single-transistor structures share the drain (Figs 1,2; ¶ [0129]). Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the multi-transistor structure of claim 21 with the semiconductor device of Hisamoto. One would have been motivated to do this in order form a memory circuit such as that disclosed by Hisamoto with the reduced area single-transistor structure of Dai (Dai; ¶ [0042]). One would have had a reasonable expectation of success because of the similar endeavors of Dai and Hisamoto and because implementing a semiconductor device circuit from one structural form or another is well-known in the art.
Regarding claim 23, Dai discloses the multi-transistor structure according to claim 21, wherein at least two single-transistor structures of the plurality of single-transistor structures have separate drains, separate channels, and separate gates (this is just two single-transistor structures according to claim 1, as applied to claim 21).
Dai does not disclose the at least two single-transistor structures share the source.
In the same field of endeavor, Hisamoto discloses a semiconductor device comprising nonvolatile memory cells using a multi-transistor structure (Fig 2; ¶ [0122-131]) comprising two single-transistor structures (MC(10),MC(20); Figs 1,2; ¶ [0129]) having have separate drains, separate channels, and separate gates (Figs 1,2; ¶ [0128-129]); and the two single-transistor structures share the source (Figs 1,2; ¶ [0129]). Accordingly, it would have been obvious for a person having ordinary skill in the art to have combined the multi-transistor structure of claim 21 with the semiconductor device of Hisamoto. One would have been motivated to do this in order form a memory circuit such as that disclosed by Hisamoto with the reduced area single-transistor structure of Dai (Dai; ¶ [0042]). One would have had a reasonable expectation of success because of the similar endeavors of Dai and Hisamoto and because implementing a semiconductor device circuit from one structural form or another is well-known in the art.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Dai, Ming-zhi (CN 108767015; hereinafter Dai), in view of Huffman; Craig Henry et al. (US 2008/0233697; hereinafter Huffman).
Regarding claim 25, Dai discloses the multi-transistor structure according to claim 21, but does not disclose the plurality of single-transistor structures comprises at least a group of single-transistor structures, and the group of single-transistor structures comprises two single-transistor structures of the plurality single-transistor structures; and the two single-transistor structures share the source and the drain while have separate channels and separate gates.
In the same field of endeavor, Huffman discloses a multi-transistor structure (MIGFET; ¶ [0017-18]) comprising two single-transistor structures (comprising two fins connected with a common source and drain); and the two single-transistor structures share the source and the drain while have separate channels and separate gates (similar to Fig 2A and ¶ [0018], but having independent (separate) gates as disclosed in ¶ [0017]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the MIGFET structure disclosed by Huffman, with the multi-transistor structure according to claim 21. One may have been motivated to do this in order to accommodate a variety of design, performance, and/or manufacturing requirements for a particular application. One would have had a reasonable expectation of success because such considerations and their implementations are well-known in the art.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang; Kuo-Nan et al. (US 2006/0084211; hereinafter Yang) in view of Rohrer; Georg (US 2010/0148257; hereinafter Rohrer).
Regarding claim 8, Yang discloses the single-transistor structure according to claim 7, wherein a distance from the channel electrode to the first side surface is greater than, less than, or equal to a distance from the channel electrode to the third side surface.
Yang does not disclose wherein H2 is less than H1.
In the same field of endeavor, Rohrer discloses a single-transistor semiconductor structure (Figs 1-3; ¶ [0022-24]) wherein a channel electrode 9 (Figs 1,3) has a width smaller than a channel contact region 16 (Figs 1,3) to which it connects. Accordingly, it would have been obvious to a person having ordinary skill in the art that the channel electrode of Yang may have a width smaller than a channel region to which it connects, that is to have thickness H2 less than thickness H1. One would have been motivated to do this because: (1) as one of various equivalent alternate connection configurations for an electrode, (2) because it is common in the art for a width or thickness of a connection electrode to be less than that to which it connects (in some cases, as one example, to allow for overlay tolerance), (3) for one a variety of design, performance, and/or manufacturing requirements for a particular application, such as, for example, to embed the conducting structure within a surrounding insulating structure (similar to the insulating region 18 comprising dielectric 20 which surrounds electrode 9 of Rohrer; Fig 3). One would have had a reasonable expectation of success because such considerations are well-known in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Erickson; Karl R. et al. (US 2013/0341733; the prior art discloses a transistor structure comprising a shared source, shared drain, and shared body contact.
Liu; Haitao et al. (US 2020/0388712; the prior art discloses a transistor structure comprising a conductive contact to the channel.
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/B.A.K./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817