DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B in the reply filed on 6/16/2026 is acknowledged.
Claims 21, 24, 31, and 38 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species E, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/16/2026.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, another implantation step implanting impurity element ions into the first and second p-type layers in a second sub-region on a side farther from the element area than a first sub-region close to the element area in the electric field relaxation region, after the first implantation step of implanting impurity element ions for inactivating a part of the acceptors in the first p-type layer and the second p-type layer by a multi-stage ion implantation method, as required by claim 34, must be shown or the feature(s) canceled from the claim(s). The drawings indicate that only one implantation step that is a multi-stage ion implantation method which No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18, 20, 23, 30, 32-34, 36-37, and 39-40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 18) As “a plurality of sub-regions” has an indeterminate number of sub-regions, “the sub-region farther from the element area” and “the sub-region closer to the element area” both lack antecedence.
During examination, “the sub-region farther from the element area” and “the sub-region closer to the element area” were read as “a sub-region farther from the element area” and “a sub-region closer to the element area”.
Claims 19-20, 23, 30, and 32-33 inherit this rejection for lack of antecedence.
(Re Claim 34) As the drawings do not demonstrate another implantation step of implanting impurity ions into the first and second p-type layers by a multi-stage ion implantation method in a second sub-region after the implantation step, and instead only show the implantation step implantation impurity element ions into a first and second sub-region as claimed, it is unclear what is required to be formed by “another implantation step”.
During examination, “another implantation step of implanting impurity element ions into the first and second p- type layers by a multi-stage ion implantation method in a second sub-region on a side farther from the element area than a first sub-region close to the element area in the electric field relaxation region, after the implantation step” was read as “during the implantation step, the impurity element ions are implanted into the first and second p-type layers by the multistage ion implantation method in a second sub-region on a side farther from the element area than a first sub-region close to the element area in the electric field relaxation region”.
Claims 36-37 and 39-40 inherit this rejection for indefiniteness.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18, 20, 23, 30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (US 2016/0163792), Nie et al. (US 2013/0161633), Ceruzzi et al. (US 2005/0202661), and Takashima et al. (US 2017/0271148).
(Re Claim 18) Oka teaches a semiconductor equipment comprising: an element area (covered by 250 down to 270 and up to the top of 260; Fig. 7) having an n-type layer (212; Fig. 7), a first p-type layer (214; Fig. 7) on the n-type layer, and a second p-type layer (215; Fig. 7) on the first p-type layer, and an electric field relaxation region surrounding the element area (the remaining part of 200 covered by the top surface of 215 that is outside of the element area, all the way down to 270; Fig. 7),
Oka has not been explicitly shown to teach the second p-type layer having an acceptor concentration higher than the first p-type layer; and wherein in the electric field relaxation region, a region containing an impurity element that inactivates a part of acceptors in the first p-type layer and the second p-type layer is provided in the first p-type layer and the second p-type layer, and wherein in the electric field relaxation region, the region containing the impurity element is formed such that a plurality of sub-regions having different impurity element concentrations are successively formed from a side close to the element area to a side far from the element area, and the sub-region farther from the element area has a higher impurity element concentration than the sub-region closer to the element area.
Nie teaches an electric field relaxation region (covered by the top surface of 802+803 down to 401; Fig. 9) surrounding an element area (the portion of the device shown in Fig. 9 that is covered by the top surface of 810 down to 401) wherein in the electric field relaxation region, a region (802+803) containing an impurity element (¶49) that inactivates a part of acceptors (“the implantation process reduces by conductivity by…decreasing the density of ionized acceptors (donors for n-type material)” (¶31)) in a p-type layer (301; Fig. 8A-9, ¶67) is provided in the p-type layer, and wherein in the electric field relaxation region, the region containing the impurity element is formed such that a plurality of sub-regions (802 and 803) having different impurity element concentrations (¶67) are successively (802 then 803, when measuring from the element area out; Fig. 9) formed from a side close to the element area (the left and right edges of 810; Fig. 9) to a side far from the element area (left and right sides of 803; Fig. 9).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form within the combined first and second p-type layer, identified as 213 in Oka, the impurity element ions and their associated first and second sub-regions 802 and 803 as described by Nie, to improve the breakdown voltage of Oka (Nie: ¶32).
Furthermore, Nie teaches implanting a sub-region (503; Fig. 5) farther from an element area (501; Fig. 6) with a higher impurity element concentration (¶52) than a sub-region (502; ¶¶51-52) closer to the element area.
A PHOSITA would find it obvious to form the sub-regions of modified Oka, as taught by Nie, such that the sub-region (Nie: 803) farther from the element area has a higher impurity element concentration than the sub-region (Nie: 802) closer to the element area, as taught by Nie’s Fig. 5 embodiment, to provide for decreasing conductivity of the p-type layers further from the element area, allowing for the breakdown voltage to be improved (“Independent of the physical mechanism, embodiments of the present invention provide a set of junction termination elements that are characterized by differing active dopant densities or concentrations, with the outer junction termination elements having a lower active dopant density than inner junction termination elements.” (¶32)).
Ceruzzi teaches forming a region (320; Fig. 3C) containing an impurity element (¶¶55, 63) after etching away side portions of a layer (308; ¶50).
A PHOSITA would find it obvious to form the region containing an impurity element between regions where the first and second p-type layer were removed, such that the impurity element containing region is formed at an edge of the p-type layers, in view of Ceruzzi, to reduce leakage current when the equipment is reverse biased (Ceruzzi: ¶36).
Takashima teaches forming a first p-type layer (30; Fig. 3A) and a second p-type layer (40; Fig. 3A).
A PHOSITA would find it obvious to form the second p-type layer having an acceptor concentration higher than the first p-type layer, as taught by Takashima (Fig. 3A), to allow for good ohmic contact between the second p-type layer and an anode (Takashima: ¶55), while having fewer lattice defects in the depletion layer between the first p-type layer and the n-type layer (Takashima: ¶55).
(Re Claim 20) Modified Oka teaches the semiconductor equipment according to claim 18, wherein the semiconductor equipment further comprises an isolation region (corresponding to 228 that is formed through etching; ¶101) and a mesa structure (portion of the device 200 that is above 228; Fig. 7) that reaches the n-type layer (Fig. 7).
Modified Oka has not been explicitly shown to teach the semiconductor equipment further comprising: an isolation region surrounding the electric field relaxation region, wherein in the isolation region, a mesa structure that reaches the n-type layer is provided, and the region containing the impurity element is provided from a surface of the n-type layer to an inside of the n-type layer.
Ceruzzi teaches forming an isolation region (region corresponding to 320A and the part of the device in Fig. 5B overlapping with 320A down to 302) in addition to a region containing an impurity element (320+320A; Fig. 5B) surrounding an electric field relaxation region (region of the device in Fig. 5B that corresponds to and is covered by 320 down to 302; Fig. 5B), wherein in the isolation region, a mesa structure (308+310+312; Fig. 5B) that reaches an n-type layer (¶47) is provided, and the region containing the impurity element is provided from a surface of the n-type layer to an inside of the n-type layer (corresponding to 320A; Fig. 5B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form an additional part of the region containing the impurity element in the isolation region of modified Oka, as taught by Ceruzzi, to provide for a further reduction in current leakage during reverse bias.
(Re Claim 23) Modified Oka teaches the semiconductor equipment according to claim 18, wherein the semiconductor equipment further comprises an isolation region (corresponding to 228 that is formed through etching; ¶101) and a mesa structure (portion of the device 200 that is above 228; Fig. 7) that reaches the n-type layer (Fig. 7).
Modified Oka has not been explicitly shown to teach the semiconductor equipment further comprising: an isolation region surrounding the electric field relaxation region, wherein in the isolation region, a mesa structure that reaches the n-type layer is provided, and the region containing the impurity element is provided from a surface of the n-type layer to an inside of the n-type layer.
Ceruzzi teaches forming an isolation region (region corresponding to 320A and the part of the device in Fig. 5B overlapping with 320A down to 302) in addition to a region containing an impurity element (320+320A; Fig. 5B) surrounding an electric field relaxation region (region of the device in Fig. 5B that corresponds to and is covered by 320 down to 302; Fig. 5B), wherein in the isolation region, a mesa structure (308+310+312; Fig. 5B) that reaches an n-type layer (¶47) is provided, and the region containing the impurity element is provided from a surface of the n-type layer to an inside of the n-type layer (corresponding to 320A; Fig. 5B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form an additional part of the region containing the impurity element in the isolation region of modified Oka, as taught by Ceruzzi, to provide for a further reduction in current leakage during reverse bias.
(Re Claim 30) Modified Oka teaches the semiconductor equipment according to Claim 18, wherein the semiconductor equipment constitutes a vertical diode (Fig. 7, ¶96), and in the element area, an anode electrode (250; Fig. 7) is formed on the second p-type layer, and a cathode electrode (270; ¶96) is formed on a back surface side (bottommost side; Fig. 7) of the n-type layer.
(Re Claim 32) Modified Oka teaches the semiconductor equipment according to Claim 18, wherein the impurity element includes at least one element of boron (B), nitrogen (N) (Nie: nitrogen; ¶¶49, 67), oxygen (O), phosphorus (P), zinc (Zn), and iron (Fe).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (US 2016/0163792), Nie et al. (US 2013/0161633), Ceruzzi et al. (US 2005/0202661), and Takashima et al. (US 2017/0271148) as applied to claim 18 above, and further in view of Kawai (US 6,111,273).
(Re Claim 33) Modified Oka teaches the semiconductor equipment according to Claim 18, but has not been explicitly shown to teach the impurity element is boron (B).
Nie teaches that the impurity element is meant to increase the resistance of the region in which it is implanted (¶31), and that such impurity elements for GaN include e.g., nitrogen, hydrogen, and helium.
Ceruzzi teaches that an impurity element implanted into a GaN layer is meant to increase the resistance, and that such an impurity element may be e.g., nitrogen, hydrogen, or boron (¶55).
A PHOSITA would find it obvious to select boron as the impurity element, in view of Nie and Ceruzzi, as boron is a known alternative dopant for GaN that increases the resistance of the regions in which it is implanted, and boron is an excellent for forming high resistance regions (Kawai: “boron (B) is best as ion species for ion implantation for making a high resistance region in a semiconductor device using GaN semiconductors” (col. 2 ln. 53-60).
Claims 34, 36-37, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (US 2016/0163792), Tomita et al. (US 2019/0305090), Mazzola et al. (US 2007/0228505), Shinagawa et al. (US 20090224240), Nie et al. (US 2013/0161633), Ceruzzi et al. (US 2005/0202661), and Takashima et al. (US 2017/0271148).
(Re Claim 34) Oka teaches a manufacturing method for a semiconductor equipment, comprising:
forming an element area (covered by 250 down to 270 and up to the top of 260; Fig. 7) and an electric field relaxation region surrounding the element area (the remaining part of 200 covered by the top surface of 215 that is outside of the element area, all the way down to 270; Fig. 7);
a step of forming an n-type layer (212; Fig. 7), a first p-type layer (214; Fig. 7) on the n-type layer, and a second p-type layer (215; Fig. 7) on the first p-type layer on a semiconductor substrate (210; Fig. 7, ¶97); and
a step of forming an electrode (250; Fig. 7) on a surface (topmost surface) of the second p-type layer in the element area.
Oka has not been explicitly shown to teach the method comprises a step of forming an n-type layer, a first p-type layer on the n-type layer, and a second p- type layer on the first p-type layer on a semiconductor substrate by epitaxial growth, the second p-type layer having an acceptor concentration higher than the first p-type layer; a step of activating acceptors of the first and second p-type layers; an implantation step of implanting impurity element ions for inactivating a part of the acceptors in the first p-type layer and the second p-type layer by a multi-stage ion implantation method into the first and second p-type layers in an electric field relaxation region surrounding an element area; another implantation step of implanting impurity element ions into the first and second p- type layers by a multi-stage ion implantation method in a second sub-region on a side farther from the element area than a first sub-region close to the element area in the electric field relaxation region, after the implantation step.
Tomita teaches forming an n-type layer (12+13; Fig. 1), a first p-type layer (14) on the n-type layer, and a second p-type layer (15) on the first p-type layer on a semiconductor substrate (11; Fig. 1) by epitaxial growth (¶¶27, 33).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the n-type, first p-type, and second p-type layers using epitaxial growth on the semiconductor substrate of Oka, as taught by Tomita, as epitaxial growth provides good control over the thickness of doped layers and where PN junctions are located (Mazzola: ¶¶66-67).
Shinagawa teaches activating acceptors using a heat treatment (¶217).
A PHOSITA would find it obvious to activate acceptors of the first and second p-type layers to allow for the acceptors to act as carriers. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Nie teaches an implantation step of implanting impurity element ions (¶67) for inactivating a part of the acceptors in a p-type layer (301; Fig. 8A; “the implantation process reduces by conductivity by…decreasing the density of ionized acceptors (donors for n-type material)” (¶31)) by a multi-stage ion implantation method (“Multiple implantations may be performed through the same mask opening, each implant being performed at a different energy…” (¶49); “Details of the ion implantation as discussed in reference to Fig. 5 above are applicable with respect to Fig. 8B” (¶67)) into the p-type layer in an electric field relaxation region (covered by the top surface of 802+803 down to 401; Fig. 9) surrounding an element area (the portion of the device shown in Fig. 9 that is covered by the top surface of 810 down to 401) wherein in the electric field relaxation region, a region (802+803) containing an impurity element (¶49) that inactivates a part of acceptors (“the implantation process reduces by conductivity by…decreasing the density of ionized acceptors (donors for n-type material)” (¶31)) in a p-type layer (301; Fig. 8A-9, ¶67) is provided in the p-type layer, and wherein in the electric field relaxation region, the region containing the impurity element is formed such that a plurality of sub-regions (802 and 803) having different impurity element concentrations (¶67) are successively (802 then 803, when measuring from the element area out; Fig. 9) formed from a side close to the element area (the left and right edges of 810; Fig. 9) to a side far from the element area (left and right sides of 803; Fig. 9).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form within the combined first and second p-type layer, identified as 213 in Oka, the impurity element ions and their associated first and second sub-regions 802 and 803 as described by Nie, to improve the breakdown voltage of Oka (Nie: ¶32).
Furthermore, Nie teaches implanting a second sub-region (503; Fig. 5) farther from an element area (501; Fig. 6) with a higher impurity element concentration (¶52) than a first sub-region (502; ¶¶51-52) closer to the element area.
A PHOSITA would find it obvious to form the sub-regions of modified Oka, as taught by Nie, such that the sub-region (Nie: 803) farther from the element area has a higher impurity element concentration than the sub-region (Nie: 802) closer to the element area, as taught by Nie’s Fig. 5 embodiment, to provide for decreasing conductivity of the p-type layers further from the element area, allowing for the breakdown voltage to be improved (“Independent of the physical mechanism, embodiments of the present invention provide a set of junction termination elements that are characterized by differing active dopant densities or concentrations, with the outer junction termination elements having a lower active dopant density than inner junction termination elements.” (¶32)).
Ceruzzi teaches forming a region (320; Fig. 3C) containing an impurity element (¶¶55, 63) after etching away side portions of a layer (308; ¶50).
A PHOSITA would find it obvious to form the region containing an impurity element between regions where the first and second p-type layer were removed, such that the impurity element containing region is formed at an edge of the p-type layers, in view of Ceruzzi, to reduce leakage current when the equipment is reverse biased (Ceruzzi: ¶36).
Takashima teaches forming a first p-type layer (30; Fig. 3A) and a second p-type layer (40; Fig. 3A).
A PHOSITA would find it obvious to form the second p-type layer having an acceptor concentration higher than the first p-type layer, as taught by Takashima (Fig. 3A), to allow for good ohmic contact between the second p-type layer and an anode (Takashima: ¶55), while having fewer lattice defects in the depletion layer between the first p-type layer and the n-type layer (Takashima: ¶55).
(Re Claim 36) Modified Oka teaches the manufacturing method for a semiconductor equipment according to claim 34, wherein in the implantation step, the impurity element ions are implanted such that a plurality of sub-regions (Nie: 802 and 803) are formed to surround the element area from a side close (right edge of sub-region 802) to the element area to a side far from the element area (left edge of Nie’s 803; see Fig. 9; also see the discussion of Nie in the rejection of claim 34).
(Re Claim 37) Modified Oka teaches the manufacturing method for a semiconductor equipment according to Claim 34, further comprising: a step of forming an isolation region (part of 200 covered by 228) by etching the first and second p-type layers in a region (the region above 228; Fig. 7) surrounding the electric field relaxation region to expose the n-type layer (¶101) after the implantation step (see the discussion of Ceruzzi’s Fig. 3C in the claim 34 rejection).
(Re Claim 39) Modified Oka teaches the manufacturing method for a semiconductor equipment according to Claim 34, wherein the impurity element ions include at least one of boron (B) ions, nitrogen (N) ions (Nie: nitrogen; ¶¶49, 67), oxygen (O) ions, phosphorus (P) ions, zinc (Zn) ions, and iron (Fe) ions.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. (US 2016/0163792), Tomita et al. (US 2019/0305090), Mazzola et al. (US 2007/0228505), Shinagawa et al. (US 20090224240), Nie et al. (US 2013/0161633), Ceruzzi et al. (US 2005/0202661), and Takashima et al. (US 2017/0271148), as applied to claim 34 above, and further in view of Kawai (US 6,111,273).
(Re Claim 40) Modified Oka teaches the manufacturing method for a semiconductor equipment according to Claim 34, but has not been shown explicitly to teach the impurity element ions are boron (B) ions.
Nie teaches that the impurity element is meant to increase the resistance of the region in which it is implanted (¶31), and that such impurity elements for GaN include e.g., nitrogen, hydrogen, and helium.
Ceruzzi teaches that an impurity element implanted into a GaN layer is meant to increase the resistance, and that such an impurity element may be e.g., nitrogen, hydrogen, or boron (¶55).
A PHOSITA would find it obvious to select boron as the impurity element, in view of Nie and Ceruzzi, as boron is a known alternative dopant for GaN that increases the resistance of the regions in which it is implanted, and boron is an excellent for forming high resistance regions (Kawai: “boron (B) is best as ion species for ion implantation for making a high resistance region in a semiconductor device using GaN semiconductors” (col. 2 ln. 53-60).
Conclusion
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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