DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8 ,10, & 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou (US Pub no. 2017/0062512 A1).
Regarding claim 8, Chou et al discloses a sensor device (100)(fig. 9a/9b/fig. 13 )comprising: a semiconductor substrate(20) that includes a plurality of photoelectric conversion elements (56)arranged for each pixel (54)and a pixel separation portion(48) having a trench(28) formed between pixels(54) to separate the pixels(54) [0041][0032]; a first insulation film (36)formed on a first surface that is one of two surfaces crossing a thickness direction of the semiconductor substrate(20) at right angles and that corresponds to a surface where the trench(28) is engraved and on an outermost
peripheral portion of the trench(28)[0030] fig. 9a; and a second insulation film(46) formed on the first insulation film(36)[0033] fig. 9a, wherein the first insulation film(36) is formed such that the trench(28) has an opening on a first surface side fig. 6 & fig. 9a, and
the second insulation film (46) is formed across an upper part of the opening of the trench(28)[0033] fig. 9a.
Regarding claim 10, Chou et al discloses A manufacturing method (fig. 9a/9b/fig. 13) comprising: a first film forming step of forming a first insulation film (36)on a first surface that is one of two surfaces crossing a thickness direction of a semiconductor substrate(20) at right angles and that corresponds to a surface where a vertical groove(28) is engraved and on a side wall portion of the vertical groove(28)[0030] fig. 6/fig. 9a,9b, the semiconductor substrate(20) being a substrate where a plurality of
photoelectric conversion elements(56) is arranged for each pixel (54) and including the vertical groove(28) separating the pixels(54)[0041][0032]; and
a second film forming step of forming a second insulation film (46)on the first insulation film(36)[0033], wherein the first film forming step forms the first insulation
film 36)such that the vertical groove(28) has an opening on a first surface side fig. 6[0030], and the second film forming step forms the second insulation
film (46)across an upper part of the opening of the vertical groove(28) fig. 9a[0033].
Regarding claim 12, Chou et al discloses wherein the first film forming step forms the first insulation film (36)by atomic layer deposition[0030], and the second film forming step forms the second insulation film (46)by chemical vapor deposition[0031-0033].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US Pub no. 2017/0062512 A1). in view of Ishiyutobuan (JPS61114548 A).
Regarding claim 1, Chou et al discloses A sensor device comprising: a semiconductor substrate (20) that includes a plurality of photoelectric conversion elements(56) arranged for each pixel (54)and a pixel separation portion (48)having a trench(28) formed between pixels(54) to separate the pixels(54)[0041][0032],
Chou et al fails to teach wherein the pixel separation portion of the semiconductor substrate is formed in directions different from cleavage directions of crystals of the semiconductor substrate.
However, Ishiyutobuan et al teaches forming isolating zones for separating pixels of an image sensor in directions different from cleavage directions of crystals of the semiconductor substrate where the isolating zone (11) is inclined relative to the cleavage plane (011) (abstract) (pp. 2 line 50 & 56-60). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Chou et al with that of Ishiyutobuan et al such that the pixel separation portion of the semiconductor substrate is formed in directions different from cleavage directions of crystals of the semiconductor substrate results to reduce the crystal defects expected to be created along the isolating zone.
Regarding claim 2, Chou et al discloses wherein the semiconductor substrate(20) is a silicon substrate[0015], and the pixel separation portion (48(28)is formed in directions different from cleavage directions [01-1], [011-], [011], [01-1-], [1-01], [101⁻], [101], [1-01-], [1-10], [11-0], [110], and [1-1-0] of silicon crystals(trench 28 has surfaces (001) [0026][0028].
Regarding claim 3, Chou et al discloses wherein the pixel separation portion(48(28)) is formed in crystal directions [001] [0026].
Regarding claim 4, Chou et al disclose wherein the trench(28) is formed in the semiconductor substrate(20) along outermost peripheral sides of a pixel (51)arrangement region that is a region where a plurality of the pixels(54) is two-dimensionally arranged fig. 9c/fig. 13.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US Pub no. 2017/0062512 A1). in view of Ishiyutobuan (JPS61114548 A). as applied to claim 4 and further in view of Watanabe (JP 2020161779 A).
Regarding claim 5,Chou et al as modified by Ishiyutobuan et al disclose all the claim limitations of claim 4 but fails to teach wherein the trench formed along the outermost peripheral sides of the pixel arrangement region has a chamfered shape at each of portions constituting four corners of the pixel arrangement region.
Watanabe et al discloses wherein the trench (331)formed along the outermost peripheral sides of the pixel(51) arrangement region has a chamfered shape at each of portions constituting four corners of the pixel arrangement region fig. 31a(para 1, pp74).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Chou et al & Ishiyutobuan et al with the teachings of Watanabe et al to curb the occurrence of defects and damage at the time of forming the grove portion and to curb the occurrence of noise charge.
Regarding claim 6, Chou et al as modified by Ishiyutobuan et al disclose all the claim limitations of claim 4 but fails to teach wherein a metal film that covers an upper part of the trench formed along the outermost peripheral sides of the pixel arrangement region is formed.
Watanabe et al discloses wherein a metal film(63) that covers an upper part of the trench formed along the outermost peripheral sides of the pixel arrangement region is formed(pp. 64, para 4; pp. 65 para 1) fig. 31a. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Chou et al & Ishiyutobuan et al with the teachings of Watanabe et al to prevent the light entering from the outside from entering a region of the adjacent pixels.
Regarding claim 7, Watanabe et al discloses wherein a metal film(63) is formed outside the pixel arrangement region in the cleavage directions of the semiconductor substrate(pp. 64, para 4; pp. 65 para 1)fig. 31a.
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fang (US Pub no. 2019/0006408 A1) in view of Hur (US pub no 2020/0219920 A1)
Regarding claim 14, Fang et al discloses A sensor device comprising:
a semiconductor substrate(110) that includes a plurality of photoelectric conversion elements(116) arranged for each pixel (116R)and a pixel separation portion (118)having a trench formed between pixels(116R) to separate the pixels[0011][0016][0029], wherein an insulation film(160) is formed at an outermost peripheral
portion of the trench(118)[0036], a metal film(170) is formed inside the insulation film(160)[0042-0043] and heat expansion material (180a) embedded inside the metal film(170) [0045]but fails to teach a similar heat expansion material that has a heat expansion characteristic similar to a heat expansion characteristic of a material constituting the semiconductor substrate
Hur et al discloses an isolation section (53) comprising a similar heat expansion material (51)that has a heat expansion characteristic similar to a heat expansion characteristic of a material constituting the semiconductor substrate(1)[0050]. Since using similar to a heat expansion characteristic of a material constituting the semiconductor substrate is one of finite solutions to help reduce a physical stress caused by a difference in thermal expansion coefficient of materials as taught by Hur et al it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Fang et al because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Regarding claim 15,Hur et al discloses wherein the semiconductor substrate(1) is a silicon substrate, and the similar heat expansion material is silicon(51)[0050].
Regarding claim 16, Hur et al discloses wherein the similar heat expansion material (51) is polysilicon[0050].
Regarding claim 17, Hur et al discloses wherein
the similar heat expansion material(51) is a material(polysilicon -51) to which
a conductive material(impurity doped) is added[0050].
.
Allowable Subject Matter
Claims 9, 11, & 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With regards to claim 9, the limitations of wherein a resin film that covers the upper part of the opening is formed between the first insulation film and the second insulation film was not found in prior art.
With regards to claim 11, the limitations of wherein the second film forming step forms the second insulation film after resist patterning is performed for a target that is
the upper part of the opening was not found in prior art.
With regards to claim 13, the limitations of wherein the first film forming step forms the first insulation film by atomic layer deposition, and the second film forming step forms the second insulation film by atomic layer deposition that has a higher film forming
temperature than a film forming temperature of the first insulation film was not found in prior art.
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Fang et al (US Pub no. 2019/0006408 A1), fails to teach wherein the wetting film becomes amorphous or microcrystalline on the insulation film in the trench and has highly oriented crystals on the insulation film outside the trench.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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