Prosecution Insights
Last updated: July 17, 2026
Application No. 18/556,509

SUBSTRATE, PACKAGE, ELECTRONIC COMPONENT, AND LIGHT EMITTING DEVICE

Final Rejection §102§112
Filed
Oct 20, 2023
Priority
Apr 26, 2021 — JP 2021-074366 +1 more
Examiner
WINTERS, SEAN AYERS
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kyocera Corporation
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
118 granted / 134 resolved
+20.1% vs TC avg
Strong +20% interview lift
Without
With
+19.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
51 currently pending
Career history
207
Total Applications
across all art units

Statute-Specific Performance

§103
84.0%
+44.0% vs TC avg
§102
14.0%
-26.0% vs TC avg
§112
1.5%
-38.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 134 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendments 2. The Amendments filed March 20th, 2026 are noted. Applicant’s amendments to the Specification to overcome the objections set forth in the Non-Final Office Action mailed 12/23/2025 are noted. Applicant’s amendment(s) to the Specification have overcome the objection(s) to the Title previously set forth in the Non-Final Office Action mailed 12/23/2025, so the objection(s) to the Title has been withdrawn. Applicant’s amendments to the claims are noted. 3. Claim 3 is canceled; Claims 12-17 are newly-added; Claims 1-2 and 4-17 remain pending in the application. 4. Claims 1-2 and 4-17 have been fully considered in examination. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 13 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Newly-added claim 13 recites the term “castellated via conductor” in line 2. The term “castellated” is not mentioned anywhere in the instant application’s Specification. Further, claim 13 recites the terms “each castellated via conductor defining a concave exposed surface on the first side surface” in lines 2-3. The term “concave” is not mentioned anywhere in the instant application’s Specification. Claim 13 fails to properly define what is meant by either of the limitation(s) “castellated via conductors” or “concave exposed surface”, and is thus rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The instant application’s specification must properly describe and support both of these terms in a manner supported by the disclosure as originally filed in order to overcome the 35 U.S.C. 112(a) rejection of claim 13. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites the limitation(s) “each castellated via conductor defining a concave exposed surface on the first side surface” in lines 2-3. Claim 13 is rendered indefinite because it is unclear what element “a concave exposed surface” belongs to in the context of claim 13. Therefore, “each castellated via conductor defining a concave exposed surface on the first side surface” has been interpreted as --- each castellated via conductor comprising a concave exposed surface on the first side surface --- Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 and 4-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohata (U.S. PG Pub No US2009/0001404A1) (of record). Regarding claim 1, Ohata teaches a substrate [see fig. 1B, 0060] comprising: a first substrate (21) fig. 1B [0064] having a first (top) surface on which an element (30) fig. 1B [0061] is to be mounted, a second (bottom) surface located opposite the first (top) surface, and a first side (left sidewall) surface connecting the first (top) surface and the second (bottom) surface; a second substrate (14) fig. 1B [0063] larger than the first substrate (21) and having a third (bottom) surface supporting the first substrate (21) and a fourth (top) surface located opposite the third (bottom) surface; and first via conductors (comprising 23A, 23B) fig. 1B [0064, 0079] configured to electrically connect the first surface (top of 21) and the second surface (bottom of 21) and exposed on the first side surface (left sidewall) of the first substrate (21) from the (level of) first surface (top of 21) to the (level of) second surface (bottom of 21). [AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (CA2)][AltContent: textbox (CA1)] PNG media_image1.png 409 756 media_image1.png Greyscale Annotated fig. 1B of Ohata Regarding claim 2, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein a cross-sectional area of the first via conductors in a cross section (CA1 versus CA2) [see annotated fig. 1B above] parallel to the first surface (top of 21) increases from the first (top of 21) surface (CA1) toward the second surface (CA2) (see cross-sectional areas CA1 versus CA2, as defined above). Regarding claim 4, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein the first substrate has a rectangular shape (21) fig. 1B [0064], and the first via conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] are located at (through) respective centers of opposite sides (left/right sides) of the first surface (top of 21). Regarding claim 5, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein the first substrate has a rectangular shape (21) fig. 1B [0064], and the first via conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] are located at (through) opposite corners (left/right corners) of the first surface (top of 21). Regarding claim 6, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein when viewed in plan, an angle between a tangent to an outer edge of each of the first via conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] are located at (through) at an intersection of the outer edge of each of the first conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] are located at (through) and a side of the first surface (top of 21) and the side of the first surface is 90 degrees +/- 20-degrees (assumed to be substantially-right angles, ~ 90 degrees due to perpendicular surfaces between 23A, 23B extending vertically and top of 21 extending horizontally). Regarding claim 7, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein at least one of the first via conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] has a portion overlapping a region where the element (30) fig. 1B [0061] is to be mounted when viewed in plan. Regarding claim 8, Ohata teaches the substrate [see fig. 1B, 0060] of claim 1. Ohata also teaches wherein the second substrate (14) fig. 1B [0063] comprises second via conductors (16) fig. 1B [0063] configured to electrically connect the third surface (bottom of 14) and the fourth surface (top of 14), and at least one of the first via conductors (comprising 23A, 23B bilayers) fig. 1B [0064, 0079] has a portion (midsection) overlapping one of the second via conductors (16) when viewed in plan. Regarding claim 9, Ohata teaches a package (comprising 1, 40) [0060-0061] comprising: substrate (1) fig. 1B [0060-0061]; and a lid (40) fig. 1B [0065]. Regarding claim 10, Ohata teaches an electronic component (comprising 1, 40, 30) fig. 1B [0060-0061] comprising: the substrate (1) fig. 1B [0060-0061] according to claim 1; and an element mounted (30 with 13) fig. 1B [0061] on the substrate (1). Regarding claim 11, Ohata teaches a light emitting device (comprising 1, 40, 30) fig. 1B [0060-0061] (comprising LED 30) comprising: the package (comprising 1, 40) [0060-0061] according to claim 9; and an element mounted (30 with 13) fig. 1B [0061] on the substrate (1), wherein the element (30) is a light emitting element (LED [0061]). Claims 1 and 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwai (U.S. PG Pub No US2020/0203266A1). Regarding claim 1, Iwai teaches a substrate (200A) fig. 11 [0096] comprising: a first substrate (100A) fig. 11 [0096] having a first (top) surface on which an element (“semiconductor chip”) [0099-0100] is to be mounted, a second (bottom) surface located opposite the first (top) surface, and a first side (left sidewall) surface connecting the first (top) surface and the second (bottom) surface (see annotated fig. 11 below); a second substrate (100 with 170) fig. 11 [0096-0098] larger than the first substrate (100A) (second substrate 100 with 170 is defined as having additional size due to the inclusion of 170, making it larger than 100A) (see annotated fig. 11 below) and having a third (top) surface supporting the first substrate (21) and a fourth (bottom) surface located opposite the third (top) surface; and first via conductors (left, right 131A of 150A) fig. 11 [0096] (formed of conductive, copper material of 130 [0097, 0100, 0103]) configured to electrically connect [0096-0098] the first surface (top of 100A) and the second surface (bottom of 100A) and exposed on the first side surface (left sidewall) of the first substrate (100A) from the first surface (top of 100A) to the second surface (bottom of 100A) (see annotated fig. 11 of Iwai below). [AltContent: arrow][AltContent: arrow][AltContent: textbox (CA2)][AltContent: textbox (CA1)][AltContent: rect][AltContent: rect] PNG media_image2.png 578 770 media_image2.png Greyscale Annotated fig. 11 of Iwai Regarding claim 12, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 1. Iwai also teaches wherein each of the first via conductors (left, right 131A of 150A) fig. 11 [0096] (formed of conductive, copper material of 130 [0097, 0100, 0103]) (formed of conductive, copper material of 130 [0097, 0100, 0103]) is continuously exposed on (supported by) the first side surface (left sidewall) from the first surface (top of 100A) fig. 11 [0096] to the second surface (bottom of 100A) along an uninterrupted (continuous) length (see annotated fig. 11 of Iwai above). Regarding claim 13, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 1. Iwai also teaches wherein the first via conductors (left, right 131A of 150A) fig. 11 [0096] comprise castellated via conductors (there is an upper portion of left/right 131A above the first substrate 110A, i.e., the upper portion could be referred to as a "castle" atop 110A), each castellated via conductor (left/right 131A of 150A) comprising a concave exposed surface on (supported by) the first side surface (left sidewall of 110A) (exposed, outer side surface of 131A in 150 concaved in /away from a direction of the first substrate 110A). Regarding claim 14, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 1. Iwai also teaches wherein the first substrate (100A) fig. 11 [0096] is a ceramic substrate (“glass” [0096] described by Iwai as a ceramic [0003. 0068]), and the first via conductors (left, right 131A of 150A) fig. 11 [0096] (formed of conductive, copper material of 130 [0097, 0100, 0103]) (formed of conductive, copper material of 130 [0097, 0100, 0103]) comprise a copper-based conductor (131A formed of 130 material Cu/copper [0103]). Regarding claim 15, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 1. Iwai also teaches wherein the first substrate is formed by singulating a larger substrate such that the first via conductors are exposed (left, right 131A of 150A) fig. 11 [0096] by a cutting process that intersects the first via conductors at the first side surface. With respect to the underlined limitation(s) above, they have been considered as “product by process” limitation(s) – process steps that do not yield an identifiable structure in the product. Note that a “product by process” limitation is directed to the product per se, no matter how actually made. See In re Thorpe et al. 227 USPQ 964 (CFAC, 1985) and the related case law cited therein, which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935. (See MPEP 2113). Regarding claim 16, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 1. Iwai also teaches further comprising: second via conductors (lower 130/131A and 140) fig. 11 [0097] configured to electrically connect (“couple”) [0097-0100] the third surface (top of 170 of 100 with 170) fig. 11 [0096-0098] and the fourth surface (bottom of 100 of 100 with 170) fig. 11 [0096-0098]. Regarding claim 17, Iwai teaches the substrate (200A) fig. 11 [0096] according to claim 16. Iwai also teaches wherein: the first side surface (left sidewall) of the first substrate (100A) fig. 11 [0096] is inclined (from bottom to midsection), and an angle between the first side surface (left sidewall of 100A in inclined portion) and the third surface (horizontal plane bottom of 100) is an obtuse angle (left sidewall of 100A from bottom of 100A to midsection clearly forms an angle greater than 90 degrees with horizontal plane), a cross-sectional area of the first via conductors (left, right 131A of 150A) fig. 11 [0096] in a cross section (horizontally) parallel to the first surface (top of 100A) increases from (CA1) [see annotated fig. 11 above] the first surface (top of 100A) toward (CA2 at) [see annotated fig. 11 above] the second surface (bottom of 100A) (based on cross-sectional areas CA1, CA2 as defined in annotated fig. 11 above), and at least one of the first via conductors (upper, left 131A) has a portion overlapping one of the second via conductors (140) fig. 11 [0097] when viewed in plan (and corresponding cross-sectional view shown in fig. 11 – evident that 140 would be partially obstructed by upper 131A in plan view). Response to Arguments Applicant's arguments filed 03/20/2026 with respect to claim 1 and the teachings of Ohata (U.S. PG Pub No US2009/0001404A1) (of record) been fully considered but they are not persuasive. With respect to Applicant’s arguments of claim 1 that “Ohata expressly distinguishes between substrate-penetrating filled vias 16 in substrate 14 and wiring layer 23 in substrate 21/contact holes 21a. That distinction is repeated in Ohata's process description. Via holes 14a are formed in first substrate 14 and then filled by copper plating to make filled vias 16. Only afterward is second substrate 21 prepared with contact holes 21a, and only afterward is metal layer 23b formed to line those contact holes and connect metal layer 23a to rear wiring pattern 15 through contact holes 21a. The resulting patterned structures are then wiring layers 23A and 23B. Thus, Ohata's own disclosure makes clear that 23A/23B are patterned wiring layers associated with second substrate 21 and contact holes 21a, not via conductors of the type recited in claim 1.” Although Ohata does not explicitly disclose contact holes 21a as “vias” and “wiring layers 23a/23b” therein as “via conductors” – one of ordinary skill in the art would recognize that the contact holes 21a formed in fig. 3A-3C of Ohata can be reasonably considered as “vias” formed through substrate 21. Further, what Ohata explicitly discloses as “via holes 14a” as formed in figs. 2A-2C in substrate 14 appear to be substantially identical to the “contact holes 21a” formed in figs. 3A-3C of Ohata – such that there is no identifiable structural difference between “via holes 14a” of Ohata and “contact holes 21a” of Ohata. Although Ohata introduces a semantic difference to differentiate holes 14a from holes 21a, one of ordinary skill in the art would consider it a broad-yet-reasonable interpretation that both of the holes 14a in substrate 14 and holes 21a in substrate 21 are “via openings/holes”. And wiring layers 23a/23b of Ohata fig. 1B [0064, 0079] are conductors in said via openings 21a, making it reasonable to consider them as “via conductors”. Further, with respect to Applicant’s argument that “Ohata does not disclose the specific side-surface exposure now emphasized in amended claim 1. Indeed, Ohata states that plating layer 50 "is neither formed on the naked surface of the first nor second substrate 14 or 21," which cuts against the Examiner's theory that the asserted conductor structure is continuously exposed along a side surface of substrate 21 in the manner now claimed. “ it is noted that the “continuously exposed along” language is not specifically recited in claim 1, which has not been amended. Rather, “continuously exposed along” is a limitation of newly-introduced claim 12, for which a new grounds of rejection for both independent claim 1 and 12 together has been presented under 35 U.S.C. 102 using Iwai (U.S. PG Pub No US2020/0203266A1). Claim 1 only requires that the first via conductors be “exposed on the first side surface” – which was addressed in the 35 U.S.C. 102 rejection of record using Ohtani. Applicant’s arguments with respect to claim(s) 12-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Remaining reference made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature substrates with via structures. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/04/2026 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Oct 20, 2023
Application Filed
Dec 23, 2025
Non-Final Rejection mailed — §102, §112
Mar 20, 2026
Response Filed
Jun 11, 2026
Final Rejection mailed — §102, §112
Jul 16, 2026
Interview Requested

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+19.9%)
3y 4m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 134 resolved cases by this examiner. Grant probability derived from career allowance rate.

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