DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 6-8 in the reply filed on 4/8/2026 is acknowledged.
Claims 1-5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/8/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishimoto (JP 2005072454 A) in view of Soda (US Pub no. 2007/0338189 A1).
Regarding claim 6, Nishimoto et al discloses A method comprising: immersing a substrate(wiring board-1) on which a plurality of circuit patterns (7)(pp. para 4;pp 13 para 1)are formed in pure water(pp. 24 para 1 lines 7-20)
;
applying voltage between the plurality of circuit patterns (7) in a state in which the
substrate (1) is immersed in the pure water (pp. 24 para 1 lines 7-20- immersed in distilled water 23C,exposed to high-humidity, & applying voltage of 5.5V);
determining the substrate to be a defective product when a tree(copper ion migration- defect) is generated in the plurality of circuit patterns (7)due to the voltage application(pp. 24 para 1 lines 20-22-defective; pp 26 para 1-copper ion migration detected)and determining the substrate (1-wiring board) to be a non-defective product when the tree is not generated(no migration pp. 10 para 4; pp 25 para 1-3; pp. 26para 1-3;pp. 27 para 1) but fails to teach a method for manufacturing a semiconductor device comprising mounting a semiconductor chip on the substrate determined to be a non-defective product.
However, Matsumoto et al discloses a radiofrequency module including a GaN based IC chip (111) mounted on a mount board 9[0050] fig. 2.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Nishimoto et al with the teachings of Matsumoto et al such that a method for manufacturing a semiconductor device comprising mounting a semiconductor chip on the substrate determined to be a non-defective product.
Results to improve the mounting reliability of the chip with a wiring board having excellent transmission characteristics at high frequencies.
Regarding claim 7, Matsumoto et al discloses wherein the semiconductor chip(111) is made with wide bandgap semiconductor (GaN based IC chip)[0050].
Regarding claim 8, Matsumoto et al discloses wherein the wide bandgap semiconductor gallium-nitride-based material(GaN based IC chip)[0050].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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