DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 3, The limitation of “all positively charged elements” is ambiguous. The specification [0063] states: For example, the material of the red photosensitive layer 111a is InAlGaN, and the proportion of In component refers to the percentage of the amount of substance of In element in the sum of the amount of substance of In element, the amount of substance of Al element, and the amount of substance of Ga element. Examiner notes that the positively charged elements are limited to In, Al , & Ga. It is unclear if al positively charged elements broadens the scope to include dopants, impurities or other cations, and appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, 7, & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1) in view of Chen (US Pub no. 2019/0172868 A1).
Regarding claim 1, Ito et al discloses An image sensor comprising: a substrate(chip ) [0070] with multiple charge storage regions(24)[0162]; a photosensitive unit (P)on the substrate(chip)[0070][[0160], wherein the photosensitive unit (P)comprises multiple photosensitive subunits[0069][0160], teach each of the multiple photosensitive subunits (P)comprises a red photosensitive layer(PD3), a green photosensitive layer(PD2), a blue photosensitive layer(PD1), and an infrared photosensitive layer(PD4) that are stacked fig. 43[0160], and the multiple photosensitive subunits(P) are respectively electrically connected to the multiple charge storage regions(24); and a lens structure (31)on a side of the photosensitive unit (P)far from the substrate(chip)[0070].
However, the sixth embodiment of Ito et al refers to a back side illuminating image sensor. Ito et al further teaches that the configuration can be applied to a front illuminating type device[0165]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the sixth embodiment of Ito et al with the teachings of a front illuminating device to achieve saturation capacity of a pixel having a FSI structure.
Ito et al fails to teach a light blocking structure between adjacent photosensitive subunits of the multiple photosensitive subunits, wherein the light blocking structure extends from a bottom of a sidewall of the red photosensitive layer of the photosensitive
subunit to a top of a sidewall of the infrared photosensitive layer of the same photosensitive subunit.
However, Chen et al discloses a light blocking structure(DTI 1002) between adjacent photosensitive subunits of the multiple photosensitive subunits(1000), wherein the light blocking structure(DTI 1002) extends from a bottom of a sidewall of the visible photodiode(912-RGB-PD) of the photosensitive subunit to a top of a sidewall of the infrared photodiode (906-IR-PD)of the same photosensitive subunit[0122-0123]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ito et al with the teachings of Ito et al with the teachings of Chen et al such that a light blocking structure between adjacent photosensitive subunits of the multiple photosensitive subunits, wherein the light blocking structure extends from a bottom of a sidewall of the red photosensitive layer of the photosensitive
subunit to a top of a sidewall of the infrared photosensitive layer of the same photosensitive subunit results to reduce crosstalk between neighboring pixels.
Regarding claim 5, Ito et al discloses multiple transistors(16a-16c and 23) on the substrate(chip), and a source region or a drain region of at least one of the multiple transistors (16a-16c and 23)is one of the multiple charge storage regions(24) ; and a metal interconnecting layer (14a-c)[0081]between the substrate (chip) and the photosensitive unit(P), wherein a metal interconnecting structure (TCV)) of the metal interconnecting layer (14a-c) is configured to electrically connect the multiple transistors(16a-16c and 23).
Regarding claim 6, Ito et al wherein at least one of the multiple transistors (102) is provided with a photosensitive processing circuit(130), and the photosensitive processing circuit (130) is configured to detect a photosensitive electrical signal generated by the photosensitive subunit(P of 1a)0070]; wherein in response to determining that a photosensitive electrical signal intensity detected by the photosensitive processing circuit (130)from the photosensitive subunit(P of 1a)is
greater than a first threshold, a blue-light incident signal is stored[0074] [0195-0196][0165];
in response to determining that a photosensitive electrical signal intensity detected
by the photosensitive processing circuit from the photosensitive subunit is
greater than a second threshold and less than or equal to the first threshold, a green-light incident signal is stored[0074] [0195-0196][0165]; in response to determining that a photosensitive electrical signal intensity detected by the photosensitive processing circuit (130)from the photosensitive subunit (P of 1a)is
greater than a third threshold and less than or equal to the second threshold, a red-light
incident signal is stored[0074] [0195-0196]; and in response to determining that a photosensitive electrical signal intensity detected by the photosensitive processing circuit (130)from the photosensitive subunit(P of 1a) is less than or equal to the third threshold, an infrared-light incident signal is stored[0074] [0195-0196].
Regarding claim 7, Ito et al discloses further comprising: a conductive plug (TCV) in the metal interconnecting layer(14a-14c), wherein a first end of the conductive plug (TCV) is connected to one of the multiple photosensitive subunits (PD1-PD4), and a second end of the conductive plug (TCV) is electrically connected to one of the
multiple charge storage regions(24)(fig. 4/fig. 43[0081][0161-0162].
Regarding claim 8, Ito et al discloses wherein the first end of the conductive plug (TCV-111) is connected to a side wall of one of the multiple photosensitive subunits(P)[0081] fig 4/fig. 43.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1)in view of Ristic (US Pub no. 2024/0136176 A1)
Regarding claim 2, Ito et al discloses all the claim limitations of claim 1 and further teaches wherein materials of the red photosensitive layer(PD3), the green photosensitive layer(PD2) , the blue photosensitive layer(PD1), and the infrared photosensitive layer (PD4)[0160] and to generate photosensitive charges based on wavelengths of received light and store the photosensitive charges in a corresponding charge storage region (24)or not generate photosensitive charges based on the wavelengths of the received light[0070] [0074] [0195-0196]but fails to teach comprise gallium- nitride -based materials containing indium element, and proportions of indium components in the red photosensitive layer, the green photosensitive layer, the blue photosensitive layer, and the infrared photosensitive layer are different,
However, Ristic et al teaches a detector for electromigration radiation such as a photodiode comprising InAlGaN that operates between 200 nm and 1770 nm by varying the atomic composition [0043]. Ristic et al explicitly discloses the capability of InAlGaN being configured to detect the visible and IR region by tuning variables x and y, which includes indium content. Since tuning the atomic composition of InAlGaN by varying the indium proportion is one finite solutions to achieve wavelengths that include visible and IR photodetecting regions as taught by Ristic et al, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try varying indium in the InAlGaN material in the red, green ,blue, and the infrared photosensitive layer of Ito et al to achieve the specific indium concentrations for each layer and to generate specific charges for each layer since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007).
Claim(s)4 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1) in view of Chen (US Pub no. 2019/0172868 A1) as applied to claim 1 and further in view of Kwon (US Pub no. 2022/0064182 A1).
Regarding claim 4, Ito et al as modified by Chen et al discloses all the claim limitations of claim 1 and further teach each of the multiple photosensitive subunits but fails to teach sequentially comprises the blue photosensitive layer, the green photosensitive layer, the red photosensitive layer, and the infrared photosensitive layer.
Kwon et al discloses a combination sensor comprising the blue photosensitive layer(200a), the green photosensitive layer(200b), the red photosensitive layer(200c), and the infrared photosensitive layer(100)[0256]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ito et al & Chen et al with the teachings of Kwon et al to achieve the optimized configuration of the sensor stack.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1) in view of Chen (US Pub no. 2019/0172868 A1) as applied to claim 1 and further in view of Luo (US Pub no. 2019/0393256 A1).
Regarding claim 10, Ito et al as modify by Chen et discloses all the claim limitations of claim 1 but fails to teach discloses wherein a material of the light blocking structure comprises a metal aluminum, or an alloy of metal aluminum.
Luo et al discloses wherein a material of the light blocking structure (2221) comprises a metal aluminum, or an alloy of metal aluminum[0035]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ito et al & Chen et al with the teachings of Luo et al to improve quality of the photodetector.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1) in view of Chen (US Pub no. 2019/0172868 A1) as applied to claim 1 and further in view of Yamaguchi (US Pub no. 2015/0349015 A1)
Regarding claim 11, Ito et al as modified by Chen et al discloses all the claim limitations of claim 1 and further teaches wherein one of the multiple charge storage regions is a floating diffusion region(24) [0162]but fails to teach
the substrate comprises a monocrystalline silicon substrate and wherein the floating diffusion region is an n- type lightly doped region formed in a p-type well.
However, Yamaguchi et al teaches a semiconductor device comprising a monocrystalline silicon substrate(1S)[0098] and wherein the floating diffusion region ( (FD))is an n- type lightly doped region formed in a p-type well (PWL)[0085][0097]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ito et al & Chen et al with the teachings of Yamaguchi et al since using monocrystalline substrate ensures carrier mobility and reduced leakage current and N-Type FD on a p-well provides signal readout capabilities.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ITO (US Pub o. 2016/0337605 A1) in view of Chen (US Pub no. 2019/0172868 A1) as applied to claim 5 and further in view of Wells (US Pub no. 2006/0261342 A1).
Regarding claim 12, Ito as modified by Chen et al discloses all the claim limitations of claim 5 but fails to teach wherein the multiple transistors comprise a transfer transistor, a reset transistor, a source follower transistor, and a row selection transistor, wherein a source electrode of the transfer transistor is electrically connected to a color
sensitive layer through a metal interconnecting structure, and a drain electrode of the
transfer transistor is a floating diffusion region; a source electrode of the reset transistor is a floating diffusion region, and a drain electrode of the reset transistor is electrically connected to a power supply voltage line through a metal interconnecting structure;
through the metal interconnecting structure, a gate electrode of the source follower
transistor is electrically connected to the floating diffusion region, a source electrode of
the source follower transistor is electrically connected to Voltage Drain Drain, and a drain electrode of the source follower transistor is electrically connected to the source electrode of the row selection transistor; and through the metal interconnecting structure, a gate electrode of the row selection transistor is electrically connected to a row scanning line for outputting a drain voltage of the source follower transistor in response to an address signal.
However, Wells et al discloses an imaging device comprising a transfer transistor(tx-16), a reset transistor(rst-22), a source follower transistor(24), and a row selection transistor(sel-26)[0029], wherein a source electrode of the transfer transistor (24)is electrically connected to a color sensitive layer(172) through a metal interconnecting structure(152), and a drain electrode of the transfer transistor (TX)is a floating diffusion region[0029]; a source electrode of the reset transistor (22)is a floating diffusion region(18), and a drain electrode (23)of the reset transistor(22) is electrically connected to a power supply voltage line(31) through a metal interconnecting structure(23)[0007];
through the metal interconnecting structure(23), a gate electrode of the source follower
transistor (24)is electrically connected to the floating diffusion region(18), a source electrode of the source follower transistor(24) is electrically connected to Voltage Drain Drain(vpix)[0007], and a drain electrode of the source follower transistor(24) is electrically connected to the source electrode of the row selection transistor(22) fig. 2; and through the metal interconnecting structure(23), a gate electrode (22)of the row selection transistor is electrically connected to a row scanning line for outputting a drain voltage of the source follower transistor in response to an address signal[0007]. It would have been obvious to one or ordinary skill in the art before the effective filing date of the invention to further modify ITO et al and Chen et al with the teachings of Wells et al such that wherein the multiple transistors comprise a transfer transistor, a reset transistor, a source follower transistor, and a row selection transistor, wherein a source electrode of the transfer transistor is electrically connected to a color sensitive layer through a metal interconnecting structure, and a drain electrode of the transfer transistor is a floating diffusion region; a source electrode of the reset transistor is a floating diffusion region, and a drain electrode of the reset transistor is electrically connected to a power supply voltage line through a metal interconnecting structure; through the metal interconnecting structure, a gate electrode of the source follower transistor is electrically connected to the floating diffusion region, a source electrode of the source follower transistor is electrically connected to Voltage Drain Drain, and a drain electrode of the source follower transistor is electrically connected to the source electrode of the row selection transistor; and through the metal interconnecting structure, a gate electrode of the row selection transistor is electrically connected to a row scanning line for outputting a drain voltage of the source follower transistor in response to an address signal results to provide circuitry for converting photons to an electrical signal.
Response to Arguments
Applicant’s arguments, see remarks, filed 5/8/2026 with respect to claim 3 have been fully considered and are persuasive. The rejection of claim 3 has been withdrawn.
Applicant's arguments with regards to claim 6 have been fully considered but they are not persuasive. Applicant argues that Ito relies on physically separate photodiodes (PD1-PD4) for different colors. However, Ito fails to disclose that the photosensitive processing circuit determines whether to store corresponding signals based on a photosensitive threshold. This distinction is fundamental and not taught or suggested by Ito. Moreover, Ito discloses a back- illuminated image sensor, and only mentions in paragraph [0165] that "the same applies to a case with a front-illuminated type device configuration." However, Ito does not specifically disclose the structure for storing corresponding photosensitive signals by a specific circuit when applied to front-illuminated devices. Therefore, claim 6 is not disclosed by Ito.
Examiner notes with regards to claim 6, Ito et al teaches that its configuration applies to front illuminating devices[0165], which has been established in the rejection of claim 1 , Therefore, the circuitry and signal processing steps described in Ito carry over and apply to the FSI embodiment. Therefore , the rejection is maintained.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
Prosecution Insights