Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings were received on 11/25/2025. These drawings are acceptable.
Claim Rejections - 35 USC § 112
Applicant’s amendments to the claims have overcome the previously presented rejections under 35 U.S.C. 112(b) and thus the rejections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (JP 2014141706 A) in view of Park (US 20180174990 A1), Kang (US 20110283034 A1), and Yamaguchi (TW 201346050 A).
Regarding claim 1, Nishimura (JP 2014141706 A) teaches an film forming apparatus 100 for forming a film on a semiconductor wafer (packaging a semiconductor) including a substrate loading section 110 (loading unit) having a space in which a mask M (member) is attached to (disposed on) a substrate S (wafer), a film forming section 200 (deposition unit) having a space in which the wafer and mask are transferred from the loading unit 110, which is connected to the deposition unit by a valve V, to form a layer patterned by the mask on the wafer, and a substrate unloading section 160 (unloading unit) having a space connected to the deposition unit 200 and wherein the substrate is transferred from the deposition unit and the mask is detached/separated from the substrate, and wherein the deposition unit includes a plurality of vapor deposition sections 210 (first and second deposition part) connected to the loading section 110 and each other (para 0002, 0018-0019, 0021, 0023-0024, 0031, 0040, 0051; Fig. 1-2).
Nishimura fails to explicitly teach packaging a semiconductor, a wafer comprising a plurality of semiconductor elements, or forming a conductive pattern layer on the wafer. However, Park (US 20180174990 A1), in the analogous art of semiconductor processing, teaches forming bumps of a semiconductor package (packaging a semiconductor) including patterned seed layers formed by using a shadow mask in a deposition process, wherein the seed layer is under bump metallization (conductive), and wherein the substrate wafer includes multiple semiconductor chips (elements) that the wafer is later divided into (Abstract, para 0013, 0028, 0035-0036, 0038, 0043). Nishimura teaches that the apparatus and methods described may be used to deposit layers on a semiconductor wafer (para 0002). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to use the apparatus of Nishimura to deposit a seed layer through a mask (conductive pattern layer) onto a substrate including multiple semiconductor chips/elements in order to package the semiconductors.
The combination of Nishimura and Park fails to explicitly teach the deposition unit includes a first deposition part to form a lower conductive pattern layer on a passivation layer formed on the wafer and a second deposition part connected to the first deposition part to form an upper conductive pattern layer, which is made of a material different from that of the lower conductive pattern layer, on the lower conductive pattern layer. However, Kang (US 20110283034 A1), in the analogous art of packaging semiconductors, teaches forming a under bump metallurgy (UBM) layer 145 on a passivation film 130 atop a semiconductor chip, wherein the under bump metallurgy layer is patterned on the substrate surface and includes a barrier layer 142 made of Ti/TiN (lower conductive pattern layer) and a seed layer 144 made of copper (upper conductive pattern layer), wherein the layers may be sequentially deposited by any of various deposition methods (para 0056-0058, 0102-0108; Fig. 2A-2B). Additionally, Yamaguchi (TW 201346050 A), in the analogous art of substrate processing, teaches a substrate and mask passing from a substrate loading section 10 through film forming sections 40a and 40b for depositing multiple different films through multiple evaporation processes (first and second deposition part) (para 0232-238; Fig. 23). Park teaches forming patterned seed layers for under bump metallization (UBM) by using a shadow mask that is subsequently removed, wherein the seed layer may be divided into a bonding layer and an electrode layer (para 0036, 0043). Because Kang and Yamaguchi teach that such deposition apparatuses and methods were operable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include a second film forming section having evaporation sources (second deposition part) connected to the first film forming section in the apparatus of Nishimura, wherein the first film forming section is configured to perform deposition of a UBM barrier layer of Ti/TiN (lower conductive pattern layer) atop a passivation layer and the second film forming section is configured to perform deposition of a UBM seed layer of copper (upper conductive pattern layer made of a material different from the lower conductive pattern layer) atop the lower conductive pattern layer with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP 2143(A)).
Regarding claim 2, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the loading unit 110 is connected to one side of the deposition unit 200 and the unloading unit 160 is connected to the opposite side of the deposition unit 200 (Nishimura para 0018, 0021, 0028; Fig. 1).
Regarding claim 9, the combination of Nishimura, Park, Kang, and Yamaguchi teaches each film formation section 200, including the second film formation section, may include a plurality of evaporation sources (210, 212) (second deposition part provided in plurality) in a row and connected to the same surface 202 of the chamber (interconnected) (Nishimura para 0023; Fig. 2).
Alternatively, or in addition, Yamaguchi teaches that a plurality of evaporation sources 41 may be included in each film forming section and each source is controlled by opening and closing the shutter via a control unit 100 (interconnected) (para 0058, 0060, 0128; Fig. 1). Because Yamaguchi teaches that such control systems were operable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include a control system for controlling the evaporation material released from each of the plurality of evaporation sources in each section, thus making the evaporation sources interconnected at least through the controller, with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP 2143(A)).
Regarding claim 11, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the apparatus includes a return section 170 (transfer unit) connecting the unloading unit 160 to the loading unit 110 so that the mask can be reused by unloading the mask from the unloading unit and loading the mask into the loading unit (Nishimura para 0029-0032; Fig. 1).
Regarding claim 12, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the apparatus includes an input mask stocker 172 (first mask storage part) connected to the substrate loading section 110 for storing unused masks to be delivered to the substrate and thus part of the “loading unit” and an output mask stocker 174 (second mask storage part) connected to the substrate unloading section 160 for storing used masks and thus part of the “unloading unit”, wherein the transfer unit 170 connects the first mask storage part 172 and the second mask storage part 174 (Nishimura para 0030-0035; Fig. 1).
Regarding claim 13, the combination of Nishimura, Park, Kang, and Yamaguchi teaches a mask cleaning mechanism (cleaning part) in the return section 170 (transfer unit) for cleaning the mask after it is unloaded from the unloading unit 160 (Nishimura para 0032).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (JP 2014141706 A) in view of Park (US 20180174990 A1), Kang (US 20110283034 A1), and Yamaguchi (TW 201346050 A), as applied to claim 1 above, and further in view of Sone (US 20110052349 A1).
Regarding claim 3, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the loading unit may include a mask load lock 173 (first loadlock part), an input mask stocker 172 (first mask storage part) in which a mask is stored, and a substrate loading section 110 (alignment part) having a space in which the wafer and mask member are transferred to and the mask is aligned with and attached (fixed) to the wafer, wherein the load lock 173 is connected to the deposition unit 200, the storage part 172, and the alignment part 110 directly or indirectly (Nishimura para 0021, 0030, 0033-0035, 0050; Fig. 1). Alternatively, the loading unit includes a loading speed adjustment unit 130 separated from the film forming unit 200 by a gate valve V (“load lock part”) connected to the deposition unit, mask storage part, and alignment part (Nishimura para 0040; Fig. 1).
The combination of Nishimura, Park, Kang, and Yamaguchi fails to explicitly teach a first wafer storage part having a space in which the wafer is stored and connected to the first loadlock part. However, Sone (US 20110052349 A1), in the analogous art of in-line deposition, teaches a substrate storing unit 27 for holding substrates prior to being transferred onto a substrate carrier for deposition (para 0044, 0053). Nishimura teaches continuously transporting substrates S into the substrate loading section 110 through a gate valve V (para 0083; Fig. 1) but is silent to where the substrates are loaded from. Therefore, because Sone teaches that such storing units were operable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to store the substrates to be supplied in Nishimura within a substrate storing unit (wafer storage part) with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP 2143(A)). Additionally, because the wafer storage part is connected to the substrate loading section/alignment part, the storage part is also indirectly connected to the loadlock part.
Claim(s) 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (JP 2014141706 A) in view of Park (US 20180174990 A1), Kang (US 20110283034 A1), and Yamaguchi (TW 201346050 A), as applied to claim 1 above, and further in view of Lee (US 20140264905 A1) and Ding (US 20140272455 A1).
Regarding claim 4, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the deposition unit 200 includes a deposition chamber (Nishimura para 0003, 0018, 0023, 0049; Fig. 2) for performing the deposition of a conductive pattern layer (Park para 0036, 0043) and substrate transport mechanism 400 (support part) installed in the deposition chamber 200 and supporting the substrate S (wafer) and mask M (Nishimura para 0022, 0044-0046; Fig. 2-3).
The combination of Nishimura, Park, Kang, and Yamaguchi fails to explicitly teach a sputtering target part installed inside the deposition chamber to face the support part and a power supply part configured to supply power to the sputtering target part. However, Lee (US 20140264905 A1), in the analogous art of deposition, teaches that a conductive layer deposited on a semiconductor, including metal layers below conductive bumps may be deposited by sputtering as an alternative to CVD or other PVD methods (para 0056, 0060-0062; Fig. 3L). Additionally, Ding (US 20140272455 A1), in the analogous art of deposition, teaches that an in-line deposition system with a transport mechanism for moving substrates may include deposition stations having target assemblies to be sputtered, wherein the target assembly includes a sputtering target facing the substrate and the transport mechanism (support part) and a power supply coupled to the target to provide power to the target (para 0033, 0069, 0072, 0078-0079; Fig. 2-3). Park teaches the conductive pattern layer may be under bump metallization (para 0036, 0043) and Nishimura teaches evaporation sources for depositing material, where the deposition sources are facing the substrate transport mechanism 400 (support part), and wherein the films may be formed by evaporation or CVD (para 0002, 0022-0024; Fig. 2). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the evaporation sources of Nishimura with sputtering target sources including a sputtering target facing the substrate and support part and connected to a power supply, as described by Ding, to deposit the conductive metallization layers of Park because this is a substitution of known elements yielding predictable results. See MPEP 2143(I)(B).
Regarding claim 5, the combination of Nishimura, Park, Kang, Yamaguchi, Lee, and Ding teaches the support part includes rollers (410, 440) and gripping member C or a belt (moving members) configured to move the substrate S and mask M through the chambers (Nishimura para 0009-0010, 0014, 0022, 0044-0046; Fig. 2-3).
Regarding claim 6, the combination of Nishimura, Park, Kang, Yamaguchi, Lee, and Ding teaches the moving member includes a plurality of rollers 410 and a gripping member C (roller plate) or a belt (conveyor belt) for transporting the mask and substrate (Nishimura para 0004, 0020, 0044-0046; Fig. 2-3). Alternatively, Ding teaches the transport mechanism 370 (support part) may be a conveyor belt or a plurality of rollers (para 0079; Fig. 3).
Regarding claim 7, the combination of Nishimura, Park, Kang, Yamaguchi, Lee, and Ding teaches the substrate S (wafer) is placed on (seated on) a (seating) surface of the rollers (410, 440) and/or the gripping member C (support part) (Nishimura para 0020, 0046, 0067, 0091; Fig. 2-3).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (JP 2014141706 A) in view of Park (US 20180174990 A1), Kang (US 20110283034 A1), and Yamaguchi (TW 201346050 A), as applied to claim 1 above, and further in view of Sone (US 20110052349 A1) and Min (KR 20200013930 A).
Regarding claim 10, the combination of Nishimura, Park, Kang, and Yamaguchi teaches the unloading unit may include an output mask stocker 174 (second mask storage part) having a space in which a mask is stored after deposition and a substrate unloading section 160 (separation part) having a space which the wafer and mask member are transferred to and the mask is separated from the wafer (Nishimura para 0021, 0031, 0033-0035, 0050; Fig. 1).
The combination of Nishimura, Park, Kang, and Yamaguchi fails to explicitly teach a second wafer storage part having a space in which the wafer is stored. However, Sone (US 20110052349 A1), in the analogous art of in-line deposition, teaches a substrate storing unit 27 for receiving substrates from an unloading chamber after deposition (para 0045, 0074). Nishimura teaches unloading substrates from the substrate unloading section 160 through a gate valve V (para 0031; Fig. 1) but is silent to where the substrates are unloaded to. Therefore, because Sone teaches that such storing units were operable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to store the processed/unloaded substrates of Nishimura within a substrate storing unit (second wafer storage part) with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP 2143(A)).
The combination of Nishimura, Park, Kang, Yamaguchi, and Sone teaches the unloading unit includes an output speed adjustment unit 140 separated from the film forming unit 200 by a gate valve V (“second loadlock part”) connected to the deposition unit 200, mask storage part 174, and separation part 160, wherein the wafer and mask are transferred from the gate valve to the separation part 160 (Nishimura para 0040; Fig. 1). Additionally, because the wafer storage part is connected to the substrate unloading section/separation part, the storage part is also indirectly connected to the loadlock part.
Alternatively, the aforementioned combination fails to explicitly teach a second loadlock part connected to the deposition unit, second wafer storage part, second mask storage part, and separation part, wherein the wafer and mask are transferred from the second loadlock part. However, Min (KR 20200013930 A), in the analogous art of substrate processing, teaches a substrate loading unit 300 and unloading unit 400 on opposite sides of a processing unit 100 including a first and second deposition unit (110, 130), wherein the loading and unloading unit where the substrate is loaded/unloaded from a tray are connected to the deposition chambers by load lock units (500, 600) (load lock part) for transferring the substrate between a vacuum state and an atmospheric state (para 0046, 0048, 0063; Fig. 2). Nishimura similarly teaches a film forming unit 200 between a loading section 110 and an unloading section 160, wherein the substrate is loaded/unloaded from a mask tray, and wherein buffer sections (120, 150) may be provided between the deposition unit 200 and the loading/unloading sections (110, 160) to absorb variations during film formation and when the substrate is removed (para 0018, 0020-0021, 0040; Fig. 1). Because Min teaches that such load lock units were operable, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include load lock units, as described by Min, as the buffer units between the film forming unit and loading/unloading units of Nishimura to transfer the substrate between atmospheric and vacuum states with a reasonable expectation of success. The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP 2143(A)). As a result, the combination of Nishimura, Park, Kang, Yamaguchi, Sone, and Min teaches a (second) load lock unit/part connected between the deposition unit and the unloading unit such that the wafer and mask are transferred to the separation part from the loadlock part and the loadlock part is connected directly or indirectly with each of the deposition unit, second wafer storage part, second mask storage part, and separation part.
Response to Arguments
Applicant's arguments filed 11/25/2025 have been fully considered but they are not persuasive.
Applicant argues that Yamaguchi teaches a first deposition part configured to form an organic film that is a semiconductor rather than a lower conductive pattern layer or upper conductive pattern layer. This argument is not persuasive because the combination with Kang and Yamaguchi results in the depositing of a Ti barrier layer (lower conductive pattern layer) and a seed layer of copper (upper conductive pattern layer) for under bump metallization, as described by Kang. Yamaguchi is merely relied upon to teach that multiple evaporation/deposition processes may be performed by transporting a substrate and mask through multiple film forming sections that are connected to each other. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include a second film forming region/section next to the first film forming region/section in the apparatus of Nishimoto for forming the barrier layer and seed layer over a passivation layer, as described by Kang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK S OTT/Examiner, Art Unit 1794