DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4).
Regarding claim 1, Jitaru discloses a switched mode power supply [e.g. fig. 6/8 (or the corresponding circuit in fig. 9/5/4] comprising an electrical circuit having a galvanic isolation [e.g. transformer] between a High Voltage (HV) circuit part [e.g. +HV circuit part connected to Vin] and a Low Voltage (LV) circuit part [e.g. the low circuit part connected to Vo], wherein said electrical circuit comprises: a substrate [e.g. PCB, see at least paras. 0013, 0015, 0035, 0083, 0110, 0112, 0123] providing said HV and said LV circuit part; an electrical component [e.g. transformer] for providing said galvanic isolation, said electrical component provided on said substrate and having a primary side connected, with a first primary terminal [e.g. the primary winding terminal] provided on a surface of said substrate, to said HV circuit part and a secondary side connected, with a first secondary terminal [e.g. the secondary winding terminal], to said LV circuit part such that a creepage distance is provided over said substrate between said first primary terminal and said first secondary terminal; and a conductive trace [e.g. the trace connected to a coil e.g. 800/896/804 fig. 8] provided on the surface of said substrate, connected with a first end to a Low Frequency (LC) voltage node [e.g. grou9nd/the node near +HV/ M fig. 5A] in said HV circuit part, wherein a frequency of a voltage potential at said LF voltage node is lower than a frequency of a voltage potential at said first primary terminal [because the flyback switch/having the similar structure], and said conductive trace provided in between said first primary terminal and said first secondary terminal thereby increasing said creepage distance between said first primary terminal and said first secondary terminal [fig. 6B/8 show the conductive trace allow to increase the creepage distance between the primary winding and the secondary winding/having the similar structure].
Jitaru does not disclose a secondary terminal provided on the surface of said substrate. However, it’s well known to provide a first coil terminal provided on a surface of said substrate, a second coil terminal provided on the surface of said substrate and a conductive trace provided on the surface said substrate. For example, Brauchler/ Fouquet/Harvey discloses a first coil terminal [see a terminal of 322/312, 422/412 Brauchler; a terminal of 28/34 fig. 5 Fouquet/ 120a/120b Harvey] provided on a surface of a substrate [e.g. 350 fig. 3/450 fig. 4 Brauchler/the substrate that coils 28/34 are on fig. 5 Fouquet/the substrate that 110a, 110b is on, Harvey], a second coil terminal [see a terminal of 312/322, 412/422 Brauchler] provided on the surface of said substrate and a conductive trace [see para. 0066, ends of coil may be located on a same conductive layer Brauchler; 30/43/45/38 fig. 5 Fouquet/e.g. 104 Harvey] provided on the surface said substrate
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Brauchler/ Fouquet/Harvey regarding a coil in order to have end of coils located on a conductive layer.
Regarding claim 2, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said Low Frequency (LF) voltage node is ground [see the fig. Jitaru].
Regarding claim 3, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said electrical component is a transformer [see the fig. Jitaru].
Regarding claim 4, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said electrical component is a transformer comprising a primary winding having said first primary terminal [e.g. the top/bottom terminal Jitaru] and having a second primary terminal [e.g. the bottom/top terminal], wherein said conductive trace is connected with said first end to said second primary terminal.
Regarding claim 5, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said conductive trace is connected with a second end to the LF voltage node [see the fig. Jitaru].
Regarding claim 8, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said substrate is a Printed Circuit Board (PCB) [Jitaru].
Regarding claim 9, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said conductive trace extends, in between said first primary terminal and said first secondary terminal, perpendicular to an imaginary direct line between said first primary terminal and said first secondary terminal [see at least fig. 6B/8 Jitaru].
Regarding claim 10, the combination discussed above discloses the switched mode power supply in accordance with claim 1, wherein said electrical circuit comprises a Switched Mode Power Supply (SMPS) [abstract Jitaru].
Regarding claim 13, the combination discussed above discloses a method of providing a switched mode power supply comprising an electrical circuit having a galvanic isolation between a High Voltage (HV) circuit part and a Low Voltage (LV) circuit part, wherein said method comprises: providing a substrate having said HV and said LV circuit part; assembling an electrical component for providing said galvanic isolation, on said substrate, said electrical component having a primary side connected, with a first primary terminal provided on a surface of said substrate, to said HV circuit part and a secondary side connected, with a first secondary terminal provided on the surface of said substrate, to said LV circuit part such that a creepage distance is provided over said substrate between said first primary terminal and said first secondary terminal; and providing a conductive trace on the surface of said substrate, connected with a first end to a Low Frequency, LF, voltage node in said HV circuit part, wherein a frequency of a voltage potential at said LF voltage node is lower than a frequency of a voltage potential at said first primary terminal, and said conductive trace provided in between said first primary terminal and said first secondary terminal thereby increasing said creepage distance between said first primary terminal and said first secondary terminal. Please see rejection of claim 1.
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4) and Udrea et al. (US 2020/0357909).
Regarding claim 11, the combination discussed above discloses the switched mode power supply in accordance with claim 10, except wherein said SMPS uses Gallium Nitride (GaN) technology. However, it’s well known that Gallium Nitride (GaN) technology provide advantages of increased power density, reduced on-resistance, and/or high frequency response. For example, Udrea discloses Gallium Nitride (GaN) technology provide advantages of increased power density, reduced on-resistance, and/or high frequency response [para. 0012].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Udrea regarding Gallium Nitride (GaN) in order to provide advantages of increased power density, reduced on-resistance, and/or high frequency response [para. 0012]
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4) and Kober et al. (US 2018/0249543).
Regarding claim 12, the combination discussed above discloses the switched mode power supply in accordance with claim 1. Jitaru does not disclose a Light Emitting Diode (LED) based lighting based on the switched mode power supply (e.g. a flyback converter Jitaru). However, it’s well known a Light Emitting Diode (LED) based lighting comprising a flyback converter. For example, Kober discloses a Light Emitting Diode (LED) based lighting comprising a flyback converter [paras. 039, 0047]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Kober regarding a LED light source in order to provide a power supply to a LED light source.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4) and Schimed (US 2004/0113736).
Regarding claim 6, the combination discussed above discloses the switched mode power supply in accordance with claim 1, except wherein said electrical component is any of a Surface-Mount Device (SMD) or a through-hole mounted device. However, it’s well-known to select Surface-Mount Device (SMD) or a through-hole mounted device mounting for an apparatus. For example, Schimed discloses to utilize Surface-Mount Device (SMD) or a through-hole mounted device mounting for a transformer apparatus [paras. 0002, 0017]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Schimed regarding an apparatus in order to utilize a well-known Surface-Mount Device (SMD) or a through-hole mounted device mounting.
Claims 14-15 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4).
Regarding claim 14, Jitaru discloses a switched mode power supply comprising an electrical circuit having a galvanic isolation between a High Voltage (HV) circuit part and a Low Voltage (LV) circuit part, wherein said electrical circuit comprises: a substrate providing said HV and said LV circuit part; a transformer for providing said galvanic isolation, said optocoupler provided on said substrate and having a primary side connected, with a first primary terminal provided on a surface of said substrate, to said HV circuit part and a secondary side connected, with a first secondary terminal, to said LV circuit part such that a creepage distance is provided over said substrate between said first primary terminal and said first secondary terminal; and a conductive trace provided on the surface of said substrate, connected with a first end to a Low Frequency (LF) voltage node in said HV circuit part, wherein a frequency of a voltage potential at said LF voltage node is lower than a frequency of a voltage potential at said first primary terminal, and said conductive trace provided in between said first primary terminal and said first secondary terminal thereby increasing said creepage distance between said first primary terminal and said first secondary terminal. Please see the rejection of claim 1.
Jitaru does not explicitly disclose an optocoupler for providing said galvanic isolation. However, it’s notoriously well-known to utilize an optocoupler for providing galvanic isolation; official notice of the foregoing fact is taken. For example, Us20140269953 by Borisov et al. discloses utilize an optocoupler for providing galvanic isolation [para. 0012]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention utilize an optocoupler for providing galvanic isolation, because the circuit needs a specific implementation and the notoriously well-known use of an optocoupler provides such an implementation.
The combination does not disclose a secondary terminal provided on the surface of said substrate. However, it’s well known to provide a first coil terminal provided on a surface of said substrate, a second coil terminal provided on the surface of said substrate and a conductive trace provided on the surface said substrate. For example, Brauchler/ Fouquet discloses a first coil terminal [see a terminal of 322/312, 422/412 Brauchler; a terminal of 28/34 fig. 5 Fouquet] provided on a surface of a substrate [e.g. 350 fig. 3/450 fig. 4 Brauchler/ the substrate that coils 28/34 are on fig. 5 Fouquet/], a second coil terminal [see a terminal of 312/322, 412/422 Brauchler] provided on the surface of said substrate and a conductive trace [see para. 0066, ends of coil may be located on a same conductive layer Brauchler; 30/43/45/38 fig. 5 Fouquet] provided on the surface said substrate Also, see the rejection of claim 1.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Brauchler/ Fouquet regarding a coil in order to have end of coils located on a conductive layer.
Regarding claim 15, the combination discussed above discloses the switched mode power supply in accordance with claim 14, wherein said Low Frequency (LF) voltage node is ground. Please see rejection of claim 2.
Regarding claim 17, Jitaru discloses a switched mode power supply comprising an electrical circuit having a galvanic isolation between a High Voltage (HV) circuit part and a Low Voltage (LV) circuit part, wherein said electrical circuit comprises: a substrate providing said HV and said LV circuit part; a transformer for providing said galvanic isolation, said capacitor provided on said substrate and having a primary side connected, with a first primary terminal provided on a surface of said substrate, to said HV circuit part and a secondary side connected, with a first secondary terminal, to said LV circuit part such that a creepage distance is provided over said substrate between said first primary terminal and said first secondary terminal; and a conductive trace provided on the surface of said substrate, connected with a first end to a Low Frequency (LF) voltage node in said HV circuit part, wherein a frequency of a voltage potential at said LF voltage node is lower than a frequency of a voltage potential at said first primary terminal, and said conductive trace provided in between said first primary terminal and said first secondary terminal thereby increasing said creepage distance between said first primary terminal and said first secondary terminal. Please see rejection of claim 1.
Jitaru does not explicitly disclose a capacitor for providing said galvanic isolation. However, it’s notoriously well-known to utilize a capacitor for providing galvanic isolation; official notice of the foregoing fact is taken. For example, US 20140269953 by Borisov et al. discloses utilize a capacitor for providing galvanic isolation [para. 0012]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention utilize a capacitor for providing galvanic isolation, because the circuit needs a specific implementation and the notoriously well-known use of a capacitor provides such an implementation.
The combination does not disclose a secondary terminal provided on the surface of said substrate. However, it’s well known to provide a first coil terminal provided on a surface of said substrate, a second coil terminal provided on the surface of said substrate and a conductive trace provided on the surface said substrate. For example, Brauchler/ Fouquet discloses a first coil terminal [see a terminal of 322/312, 422/412 Brauchler; fa terminal of 28/34 fig. 5 Fouquet] provided on a surface of a substrate [e.g. 350 fig. 3/450 fig. 4 Brauchler], a second coil terminal [see a terminal of 312/322, 412/422 Brauchler] provided on the surface of said substrate and a conductive trace [see para. 0066, ends of coil may be located on a same conductive layer Brauchler; 30/43/45/38 fig. 5 Fouquet] provided on the surface said substrate
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Brauchler/ Fouquet regarding a coil in order to have end of coils located on a conductive layer.
Regarding claim 18, the combination discussed above discloses the switched mode power supply in accordance with claim 17, wherein said Low Frequency (LF) voltage node is ground. Please see rejection of claim 2.
Claims 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jitaru et al. (US 2020/0211762) in view of Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4) and Kober et al. (US 2018/0249543).
Regarding claim 16, the combination discussed above discloses the switched mode power supply in accordance with claim 14. the combination does not disclose a Light Emitting Diode (LED) based lighting based on the switched mode power supply (e.g. a flyback converter Jitaru). However, it’s well known a Light Emitting Diode (LED) based lighting comprising a flyback converter. For example, Kober discloses a Light Emitting Diode (LED) based lighting comprising a flyback converter [paras. 039, 0047]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Kober regarding a LED light source in order to provide a power supply to a LED light source. Please see also rejection of claim 12.
Regarding claim 19, the combination discussed above discloses the switched mode power supply in accordance with claim 17. the combination does not disclose a Light Emitting Diode (LED) based lighting based on the switched mode power supply (e.g. a flyback converter Jitaru). However, it’s well known a Light Emitting Diode (LED) based lighting comprising a flyback converter. For example, Kober discloses a Light Emitting Diode (LED) based lighting comprising a flyback converter [paras. 039, 0047]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Jitaru in accordance with the teaching of Kober regarding a LED light source in order to provide a power supply to a LED light source. Please see also rejection of claim 12.
Allowable Subject Matter
Claims 7 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection rely on a new reference, Brauchler et al. (US 2015/0171934) (or Fouquet et al. US 8,093,983; or Harvey US 7,468,547 figs, 1, 4), which was not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant argues:
‘First, Brauchler does not describe or suggest "a first secondary terminal provided on the surface of said substrate," as recited in claim 1 and similar recitations in claims 13, 14, and 17. (emphasis added) The Office Action asserts that Brauchler describes or suggests this features at "[see a terminal of 322/312, 422/412 Brauchler...]" and "[see para. 0066, ends of coil may be located on a same conductive layer Brauchler...]" (Office Action, Page 4.) Brauchler states "First IC die 310 includes at least one coil 312..." (Brauchler at [0044]) and "Similar to first IC die 310, second IC die 320 includes at least one coil 322 (e.g., coil 154, FIG. 1)..." (Brauchler at [0045].) Brauchler also states "When inductive coupling substrate 700 is incorporated into an inductive communication device (e.g., device 130, 300, 400, FIGS. 1, 3, 4), coil 740 may be aligned with a corresponding coil of an underlying first IC die (e.g., coil 144, 312, 412, of IC die 140, 310, 410, FIGS. 1, 3, 4), and coil 750 may be aligned with a corresponding coil of an underlying second IC (e.g., coil 154, 322, 422, of IC die 150, 320, 420, FIGS. 1, 3, 4)..." (Brauchler at [0074].)
In Brauchler, coil 312 or coil 412 is disposed on a first IC die 310, 410, respectively, and coil 322 or coil 422 is disposed on a second IC die 320, 420, respectively. Here, coil 312 and coil 322 are disposed on two different surfaces, a surface of first IC die 310 and a surface of second IC die 320, respectively. Similarly, coil 412 and coil 422 are disposed on two different surfaces, the surface of first IC die 410 and the surface of second IC die 420, respectively. In contradistinction, claim 1 recites, "...with a first primary terminal provided on a surface of said substrate..." and "...a first secondary terminal provided on the surface of said substrate..." (emphasis added). In other words, "a first primary terminal" and "a first secondary terminal" are on a surface of the same substrate.
Brauchler also states "In other embodiments, coil 640 may be formed using fewer or more than three conductive layers, and/or the ends of coil 640 may be located on a same conductive layer." (Brauchler at [0066].) FIG. 6 of Braucher shows "...a cross-sectional, side view of an integrated circuit die that may be used in an inductive communication device..." (Brauchler at [0011].) In FIG. 6, "...IC die 600 includes a coil 640 (e.g., one of coils 144, 152, 244, 312, 322, 412, 512, FIGS. 1-3, 5)..." and "coil 640 ... includes multiple substantially-concentric conductive rings 641, 642, 643...." (Brauchler at [0066].) As described above, the Office Action, page 4, states "see a terminal of 322/312, 422/412" and therefore, the Examiner contends that each of coil 312, 322, 412, 422, is a terminal. As shown above, Brauchler merely states "...ends of coil 640 may be located on a same conductive layer..." In other words, Brauchler is discussing each coil (i.e. a terminal in claim 1) and does not describe or suggest "...with a first primary terminal provided on a surface of said substrate..." and "...a first secondary terminal provided on the surface of said substrate...," as recited in claim 1. (emphasis added).’
However, coil 312 and coil 412 are disposed in an IC die 310 and an IC die 410, respectively, and coil 322 or coil 422 are disposed in a IC die 320 and a IC die 420, respectively. In addition, either fig. 3 or fig. 4 shows coil 312 and coil 322 are disposed on substrate 350 or 450. For example, see para. 0042 of US 2019/0372453 by Lee. Accordingly, a first primary terminal is provided on a surface of the substate and a first secondary terminal is provided on a surface of the substate.
Applicant argues:
‘Second, Fouquet does not describe or suggest "a first secondary terminal provided on the surface of said substrate," as recited in claim 1 and similar recitations in claims 13, 14, and 17. (emphasis added.) The Office Action asserts that Fouquet describes or suggests this features at "[...a terminal of 28/34 fig. 5 Fouquet...]" and "[...30/43/45/38 fig. 5 Fouquet...]." (Office Action, Page 4). Fouquet states "Therefore, one might create a coil transducer to fit in such a space that looks like that shown in FIG. 3, in which the input and output coils 28 and 34 in coil transducer 10 fit within an 8 mil space between lead frames 56 and 58." [Fouquet at col. 5, lines 17-21.] Claim 1 recites "an electrical component...with a first primary terminal provided on a surface of said substrate... with a first secondary terminal provided on the surface of said substrate". Even if, arguendo, the Examiner's position in the Office action were accepted, which Applicant does not concede, if coil 28 is "a first primary terminal" and coil 34 is "a first secondary terminal", or vice versa, both coil 28 and coil 34 not part of "an electrical component" and are in fact part of two, separate and distinct, electrical components.
Fouquet also states "First electrically conductive coils 28 a-28 d are disposed near or on first sides 24 a-24 d of dielectric barriers 22 a-22 d of each coil transducer, first leads 30 a- 30 d and 32 a-32 d extending between first coils 28 a-28 d and wire bond pads corresponding thereto (40 a-40 d and 42 a-42 d)." (Fouquet at [col. 7, lines 27-32].) Here, first leads 30a - 30d are merely extensions of coils 28a - 28d, respectively, and would suffer from the same deficiencies described above by being not part of "an electrical component" and are in fact part of two, separate and distinct, electrical components, in other words coils 28a - 28d. Similarly, Fouquet states "Second electrically conductive coils 34 a-34 d are disposed near or on second sides 26 a-26 d of dielectric barriers 22 a-22 d of each coil transducer, second leads 36 a- 36 d and 38 a-38 d extending between second coils 34 a-34 d and wire bond pads corresponding thereto (44 a-44 d and 46 a-46 d), where dielectric barriers 22 a-22 d are disposed between first and second coils 28 a-28 d and 34 a-34 d." (Fouquet at [col. 7, lines 32-38].) Here, second leads 38a - 38d are merely extensions of coils 34a - 34d, respectively, and would suffer from the same deficiencies described above by being not part of "an electrical component" and are in fact part of two, separate and distinct, electrical components, in other words coils 34a - 34d.
Finally, Fouquet states "Bus leads 43 and 45 run along the outer edges to deliver a supply voltage, a ground signal or a control signal to a relatively distant silicon IC." (Fouquet at [col. 5, lines 46-48].) Here, bus leads 43 and 45, as shown in FIG. 5, would suffer from the same deficiencies described above by being not part of "an electrical component" and are in fact part of two, separate and distinct, electrical components, bus leads 43 and 45, respectively.’
However, a coil can be considered as an electric component. In addition, Coils 28 and 34 can be considered as a component, e.g. a coil transducer/a transformer. In addition, the matched items were a terminal of 28/34. The office action did not indicate 28/34 is/are a terminal. In addition, fig. 5 of Fouquet shows a substrate that coils 28/34 are on. Also, Fouquet discloses “Note that the metal coil turns in coil transducer 10 shown in FIG. 5 do not occupy the full footprint of the flex substrate into which coils 28 and 34, wirebond pads 40 and 42, and bus trace 43 are formed. (Note further that coil transducer 10 may be formed of materials other than flex.) See Col. 5, lines 40-45. In addition, “a” or “an” does not exclude a plurality. See para. 0070 of the current application.
Applicant argues:
‘Third, Harvey does not describe or suggest "a first secondary terminal provided on the surface of said substrate," as recited in claim 1 and similar recitations in claims 13, 14, and 17. (emphasis added.) The Office Action asserts that Harvey describes or suggests this features at "[...120a/120b Harvey]", "[...the substrate that 110a, 110b is on, Harvey]", and "[...e.g. 104
Harvey]." (Office Action, Page 4.) Harvey states "The digital isolate includes a split leadframe 104 , including a first leadframe portion 104 a and a second leadframe portion 104 b." (Harvey at [col 2., lines 62-64].) Harvey also states "Each leadframe portion 104 a and 104 b includes a corresponding main body 110 a and 110 b and a corresponding finger 120 a and 120 b." (Harvey at [col 3., lines 3-5].) In other words, finger 120 a is a part of main body 110 a which is part of a first leadframe portion 104 a and finger 120 b is part of main body 110 b which is part of a second leadframe portion 104 b. Claim 1 recites "an electrical component...with a first primary terminal provided on a surface of said substrate...with a first secondary terminal provided on the surface of said substrate". Even if, arguendo, the Examiner's position in the Office action were accepted, which Applicant does not concede, if finger 120 a is "a first primary terminal" and finger 120 b is "a first secondary terminal", or vice versa, both finger 120 a and finger 120 b are not part of "an electrical component" and are in fact part of two, separate and distinct, electrical components, leadframe portion 104 a and leadframe portion 104 b, respectively.’
However, as discussed in the second, finger 120 a is "a first primary terminal" and finger 120 b” is "a first secondary terminal", or vice versa, both finger 120 a and finger 120 b can be considered as part of "an electrical component", i.e. "finger transformer". In addition, “a” or “an” does not exclude a plurality. See para. 0070 of the current application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK C CHEN/Primary Examiner, Art Unit 2836
Prosecution Insights