Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 18 is rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without “the elements that make a vertical power device, e.g., semiconductor substrate, P-N Junction/Body Region: Crucial for forming the depletion region in blocking state, source layer, bottom drain layer, contacts and electrodes”, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976).
A single layer, e.g., a drift layer and its doping concentration is not deemed to include enough device elements to constitute a vertical power device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. (US 2016/0005843 A1) in view of Chang et al. (US 2021/0376090 A1).
Regarding independent claim 10: Hirabayashi (e.g., Figs. 2-8) a method for producing vertical power semiconductor components, the method comprising the following steps:
applying a first side of a silicon wafer ([0012], [0063] and [0067]: upper side of wafer 10/50/60 as an SOI wafer) onto a subcarrier wafer ([0061]: 70),
wherein a front side of the vertical power semiconductor components (Fig. 2) is arranged on the first side of the silicon wafer (Fig. 2; vertical device is on the front side of silicon wafer 10) and the front side of the vertical power semiconductor components includes
a buffer layer ([0065]-[0066]: layer 50 is used to protect wafer 10 during implant, thus it functions as a buffer layer) and
a drift layer ([0059]: 12a);
grinding the silicon wafer ([0015], [0060], [0063]) to a specific thickness;
dry etching the silicon wafer ([0063]: dry etching used during etching of bottom layer of substrate);
etching the buffer layer ([0067]: 50);
implanting ions ([0066]) into the drift layer,
wherein a contact semiconductor layer ([0081] and [0088]: 30) is formed;
applying a metal layer ([0074]-[0075] and [0085]: 32) onto the contact semiconductor layer; and
removing the subcarrier wafer ([0075]: subcarrier wafer 70 is removed).
Hirabayashi does not expressly teaches generating an ohmic contact by applying a metal layer onto the contact semiconductor layer.
Chang teaches (e.g., Figs. 1-3A) a method for producing vertical power semiconductor components, the method comprising the following steps:
generating an ohmic contact ([0013], [0018] and [0029]) by applying a metal layer ([0017]-[0018] and [0029]: element 114 forms ohmic contact with the substrate; the ohmic contact is formed between a metal and a semiconductor; thus, the limitation requirement is met) onto a contact semiconductor layer ([0019] and [0028]-[0029]: 102).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Hirabayashi, the method comprising generating an ohmic contact by applying a metal layer onto the contact semiconductor layer, as taught by Chang, for the benefits of creating a low-resistance electrical connection between the metal and a semiconductor that allows current to flow easily in both directions, by creating a very thin depletion layer that enables quantum tunneling of charge carriers, ensuring minimal voltage drop and efficient power delivery in electronic devices.
Regarding independent claim 13: Hirabayashi (e.g., Figs. 2-8) a method for producing vertical power semiconductor components, comprising the following steps:
applying a first side of a silicon wafer ([0012], [0063] and [0067]: upper side of wafer 10/50/60 as an SOI wafer) onto a subcarrier wafer ([0061]: 70),
wherein a front side of the vertical power semiconductor components (Fig. 2) is arranged on the first side of the silicon wafer (Fig. 2; vertical device is on the front side of silicon wafer 10) and the front side of the vertical power semiconductor components includes
a buffer layer ([0065]-[0066]: layer 50 is used to protect wafer 10 during implant, thus it functions as a buffer layer) and
a contact semiconductor layer ([0081] and [0088]: 30);
grinding the silicon wafer ([0015], [0060], [0063]) to a specific thickness;
dry etching the silicon wafer ([0063]: dry etching used during etching of bottom layer of substrate);
etching the buffer layer ([0067]: 50);
applying a metal layer ([0074]-[0075] and [0085]: 32) onto the contact semiconductor layer; and
removing the subcarrier wafer ([0075]: subcarrier wafer 70 is removed).
Hirabayashi does not expressly teaches generating an ohmic contact by applying a metal layer onto the contact semiconductor layer.
Chang teaches (e.g., Figs. 1-3A) a method for producing vertical power semiconductor components, the method comprising the following steps:
generating an ohmic contact ([0013], [0018] and [0029]) by applying a metal layer ([0017]-[0018] and [0029]: element 114 forms ohmic contact with the substrate; the ohmic contact is formed between a metal and a semiconductor; thus, the limitation requirement is met) onto a contact semiconductor layer ([0019] and [0028]-[0029]: 102).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Hirabayashi, the method comprising generating an ohmic contact by applying a metal layer onto the contact semiconductor layer, as taught by Chang, for the benefits of creating a low-resistance electrical connection between the metal and a semiconductor that allows current to flow easily in both directions, by creating a very thin depletion layer that enables quantum tunneling of charge carriers, ensuring minimal voltage drop and efficient power delivery in electronic devices.
Regarding claim 14: Hirabayashi and Chang teach the claim limitation of the method according to claim 13, on which this claim depends.
wherein the vertical power semiconductor component includes gallium nitride or silicon carbide (Hirabayashi: [0012]: silicon carbide).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. (US 2016/0005843 A1) in view of Chang et al. (US 2021/0376090 A1) as applied above and further in view of Pala et al. (US 2022/0059706 A1).
Regarding claim 12: Hirabayashi and Chang teach the claim limitation of the method according to claim 10, on which this claim depends.
Hirabayashi as modified by Chang does not expressly teach that the ion implantation includes silicon-containing dopants.
Pala teaches (e.g., Fig. 2) a method comprising forming a drift layer ([0028])
ion implantation including silicon-containing dopants ([0026]-[0028]: silicon dopant for n-type drift layer).
Silicon is an art recognized suitable material as a dopant.
Applicant is reminded that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol.
"Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). MPEP 2144.07.
Therefore, It would have been obvious to a person of ordinary skill in the at the time of the effective filing date to include in the method of Hirabayashi as modified by Chang, the method of performing ion implantation including silicon-containing dopants in the drift layer, as taught by Pala, for the benefits of controlling the current flow through the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. (US 2016/0005843 A1) in view of Chang et al. (US 2021/0376090 A1) as applied above and further in view of Mahler et al. (US 2010/0059864 A1).
Regarding claim 15: Hirabayashi and Chang teach the claim limitation of the method according to claim 13, on which this claim depends.
Hirabayashi as modified by Chang does not expressly teach that the subcarrier wafer includes glass or silicon;
Mahler teaches (e.g., Fig. 6) a method comprising forming a subcarrier wafer including glass ([0035]: 202).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Hirabayashi as modified by Chang, the method wherein the subcarrier wafer includes glass, as taught by Mahler, because glass is an art recognized material used for subcarriers; furthermore, the glass is strong enough to serve as a support during manufacturing and wafer handling, thus avoiding device mechanical damage.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hirabayashi et al. (US 2016/0005843 A1) in view of Chang et al. (US 2021/0376090 A1) as applied above and further in view of Kim (US 2005/0074947 A1).
Regarding claim 16: Hirabayashi and Chang teach the claim limitation of the method according to claim 13, on which this claim depends.
Hirabayashi as modified by Chang does not expressly teach that the buffer layer is etched wet-chemically or using a chlorine-based dry-etching process.
Kim teaches a buffer layer is wet-chemically etched (Claim 7).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Hirabayashi as modified by Chang, the method of wet-chemically etching the buffer layer, as taught by Kim, for the benefits of removing the remaining residual particle and thus improving the reliability of the device.
Allowable Subject Matter
Claims 11 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method for producing vertical power semiconductor components, the method comprising the following steps:
“wherein the ion implantation has a dopant concentration greater than 1e19 cm^-3”.
Regarding claim 17: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method for producing vertical power semiconductor components, the method comprising the following steps:
“wherein the specific thickness is between 100 µm and 500 µm.”
Claim 18 would be allowable should the 35 U.S.C. 112(a) rejection overcome.
The following is an examiner’s statement of reasons for allowability:
Regarding claim 18: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a vertical power semiconductor component, comprising:
“a drift layer, wherein ions are implanted in the drift layer and the ions includes a dopant concentration greater than 1e19 cm^-3”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812