DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 16-31, in the reply filed on February 23, 2026 is acknowledged.
Claims 32 and 33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 23, 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 25, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on December 13, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on February 9, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17 and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the control electrode" in line 1 of claim 17. There is insufficient antecedent basis for this limitation in the claim.
Claim 25 recites the limitation "the gate electrode" in line 1 of claim 25. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16, 21-24, 26, 29, and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al (US Pub 2008/0142837).
In re claim 16, Sato et al discloses a vertical transistor (i.e. 220), comprising: an outer region (i.e. where the Si substrate 214 is present) and a membrane region (i.e. region where the back-side trench 217 is present), wherein at least a portion of a semiconductor substrate (i.e. 214) is arranged in the outer region, wherein the semiconductor substrate is structured in such a way that a rear trench (i.e. 217) is arranged in the membrane region, wherein the rear trench is free of semiconductor substrate (i.e. by definition, the trench would not contain the semiconductor substrate); a masking layer (i.e. 227) in the outer region and/or in the membrane region; and a layer stack (i.e. 223, 222) in the membrane region, wherein the layer stack includes at least one drift layer (i.e. 222), at least one component-defining layer system (i.e. 211, 223), and at least one control terminal (i.e. 219 or 229, is controlled by an anode and/or cathode); wherein the masking layer (i.e. 227) is configured such that a region on the masking layer is substantially free of the layer stack (i.e. see at least Figure 18b) so that a lateral extension of the layer stack is adjusted using the masking layer (i.e. 227) (i.e. see at least Figures 16-18).
In re claim 21, Sato et al discloses further comprising: a terminal contact (i.e. 215) arranged in the rear trench and electrically coupled to the component-defining layer system by the drift layer (i.e. see at least Figure 17).
In re claim 22, Sato et al discloses wherein the masking layer (i.e. 227) is arranged directly on the semiconductor substrate (i.e. see at least Figure 18a).
In re claim 23, Sato et al discloses wherein the layer stack includes a multitude of control terminals arranged in the membrane region above a common rear trench (i.e. see at least Figures 17 and 18).
In re claim 24, Sato et al discloses wherein the layer stack is a first layer stack (i.e. leftmost stack is considered the first layer stack in Figures 17 and 18), and wherein a second layer stack (i.e. rightmost stack is considered the second layer stack in Figures 17 and 18), which includes the at least one drift layer (i.e. 222), at least one component-defining layer system (i.e. 211, 223), and at least one control terminal (i.e. 219 or 229), and the first layer stack are arranged in the membrane region above a common rear trench, wherein the first layer stack is laterally separated from the second layer stack (i.e. see at least Figures 17 and 18).
In re claim 26, Sato et al discloses wherein the masking layer (i.e. 227) is arranged in the membrane region, and the second layer stack is separated from the first layer stack using the masking layer in the membrane region (i.e. see at least Figures 17 and 18).
In re claim 29, Sato et al discloses further including a filler material (i.e. 228) on or above the masking layer, wherein the filler material at least partially contacts the layer stack laterally (i.e. see at least Figures 17 and 18).
In re claim 31, Sato et al discloses wherein the semiconductor substrate includes or is formed from silicon (i.e. see at least paragraph 0175) and the component-defining layer system includes or is formed from gallium nitride (i.e. see at least paragraph 0189).
Allowable Subject Matter
Claims 17 and 25 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 18-20, 27, 28, and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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/ANTHONY HO/Primary Examiner, Art Unit 2817