DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 13-19, in the reply filed on 3/12/2026 is acknowledged.
Claims 20-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/12/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 13, the limitation “[a] method for manufacturing an electronic circuit with micro-bumps for interconnection by modifying metalization steps in the used CMOS technology” does not appear to have support in the originally filed disclosure. Specifically, the scope of “modifying metalization steps” is so broad as to include myriad “modifications” which are not disclosed or supported by the single embodiment disclosed. Additionally, there does not appear to be any disclosure related to the “by modifying metalization steps in the used CMOS technology.”
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 13-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, the claim recitation “A method for manufacturing an electronic circuit with micro-bumps for interconnection by modifying metalization steps in the used CMOS technology, including at least a dielectric layer, a metal layer and a via layer” is unclear as to what constitutes the preamble and as to what constitutes the body of the claim.
Regarding claim 13, the limitation “for interconnection,” is unclear as to what is “for interconnection,” (i.e. the method, the circuit, or the micro-bumps).
Regarding claim 13, the limitation “by modifying metalization steps in the used CMOS technology” is unclear as to what is required by “the used CMOS technology.” It is further unclear as to what is required by “modifying metalization steps in the used CMOS technology, or what that modification may or may not include.
Regarding claim 13, the limitation “including at least a dielectric layer, a metal layer and a via layer” is unclear as to what includes the at least a dielectric layer, a metal layer and a via layer (i.e. the method, the circuit, the interconnection, the metalization steps, or the used CMOS technology).
Regarding claim 14, the parentheticals of reference characters which include “…” are unclear as to what additional reference characters may or may not be included in the scope of the claim.
Regarding claim 14, the limitations “metal connections,” “main layer,” “interconnect metals,” are unclear as to how they are related to the “a metal layer” recited in claim 13.
Regarding claim 14, the limitation “comprising a main layer” is unclear as to what element comprises the main layer. Specifically, it appears to be referring to the metal deposition, however it is unclear as to how a deposition can comprise a layer.
Regarding claim 14, the limitation “such as titanium nitride” renders the claim indefinite because it is unclear whether the limitations following the phrase “such as” are part of the claimed invention. See MPEP § 2173.05(d).
Regarding claim 14, the limitation “ a layer of dielectric material” is unclear as to how it is related to the “at least a dielectric layer” recited in claim 13.
Regarding claim 14, the limitation “the dielectric material” is unclear as to how it is related to the previously recited “layer of dielectric material,” and the “at least a dielectric layer” recited in claim 13.
Regarding claim 14, the limitation “these passages” is unclear as to which passages the limitation refers.
Regarding claim 14, the limitation “vias” is unclear as to how it is related to the “via layer” recited in claim 13.
Regarding claim 14, the limitation “the levels” is unclear as to which levels it refers and as to how it is related to the previously recited “first level.”
Regarding claim 14, the limitation “steps (a) to (d) are repeated to form the metal connections (P, P',...) at different depths” is unclear as to how the steps are repeated to form “the metal connections,” when the “metal connections” are understood to be formed in the first, previously recited, performing of step (a). It is further unclear as to how “different depths” is related to the “first level” and “the levels.”
Regarding claim 14, the limitation “interconnection vias” is unclear as to how it is related to the previously recited “vias” and the “via layer” recited in claim 13.
Regarding claim 14, the limitation “the circuit” is unclear as to how it is related to the previously recited “electronic circuit.”
Regarding claim 14, the limitation “an iteration of step (a)” is unclear as to how it is related to the “steps (a) to (d) are repeated.”
Regarding claim 14, the limitation “an iteration of step (a) in order to form, simultaneously: * a set of individualized conductive elements constituting interconnection studs (PL) of the electronic circuit with homologous conductive studs of another circuit by bringing together and pressing the circuits and direct solderless contact, and * a set of connecting studs (PB) for bonding wires,” is unclear as to how iteration of step (a) can achieve “with homologous conductive studs of another circuit by bringing together and pressing the circuits and direct solderless contact.” It is further unclear as to what is required by iteration of step (a) since step (a) results in metal connections in a first level in the substrate, however the limitation appears to require step (a) to form studs which cannot be understood to be in a first level of the substrate. It is additionally unclear as to which circuits “the circuits” refers.
Regarding claim 14, the limitations “interconnection studs,” “homologous conductive studs of another circuit,” “by bringing together and pressing the circuits and direct solderless contact,” and “a set of connecting studs (PB) for bonding wires,” are unclear as to how they are related to “an electronic circuit with micro-bumps for interconnection.
Regarding claim 14, the limitations “by bringing together and pressing the circuits and direct solderless contact,” and “a set of connecting studs (PB) for bonding wires,” are unclear as to how they are related to each other and compatible with each other. Specifically, it would not be understood that a metallization layer of a circuit would be both solderless bonded and also have bonding wires.
Regarding claim 15, the limitation “wherein it further comprises,” is unclear as to what “it” refers to.
Regarding claim 15, the limitation “an iteration of steps (b) to (d) to form a set of individualized conductive elements (P"') topped by columns (CO) of the interconnect metal (300) contained in a layer (140) of dielectric material,” is unclear as to how it is related to the previously recited repeating of steps (a) to (d). It is further unclear as to the “the interconnect metal,” which is understood as already having been formed in the first step of (d), is topping elements formed in an iteration of (b) to (d). It is further unclear as to how “a layer of dielectric material,” is related to the “layer of dielectric material,” of claim 14 and the “at least a dielectric layer” of claim 13.
Regarding claim 15, the limitation “homologous conductive studs of the other circuit,” is unclear as to how it is related to the “homologous conductive studs of another circuit,” recited in claim 14.
Regarding claim 18, the limitation “the dielectric material” unclear as to how it is related to the “layer of dielectric material,” of claim 14 and the “at least a dielectric layer” of claim 13.
Regarding claim 19, the limitation “wherein step of removing the secondary layer (222F) at the connecting studs is implemented before the iteration of step (a),” is unclear as to how removing the secondary layer at the connecting studs can be implemented before the iteration of step (a) when the iteration of step (a) is recited as the means of forming the connecting studs.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
It is noted that the claims have not been rejected over the prior art because, in light of the 35 U.S.C. 112 rejections supra, there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claims; hence, it would not be proper to reject the claims on the basis of prior art. As stated in In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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