DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibayama et al. (Shibayama, US 2015/0195935).
Regarding claim 1, Shibayama shows a semiconductor package ( FIG. 1) comprising: a base (bottom plate 1 in FIG. 1 and [0033]) comprising a first surface (top surface of plate 1) comprising a first side and a second side (side surface 3a and 3b) coupled to the first side (surface 3a); a wiring (terminal 4a/4b) laminate portion located on the first surface, extending along the first side of the first surface (see FIG. 2 with respect to FIG. 1), and comprising a second surface extending along the second side; and a peripheral wall portion (see FIG. 2 with respect to FIG. 1), together with the wiring laminate portion (terminal 3), surrounding the first surface, wherein the wiring laminate portion comprises a plurality of insulation layers (insulator 3 and [0058]) laminated in a layered structure (FIG. 2), at least two first wiring conductors located on different insulation layers of the plurality of insulation layers ( insulator 3), and a first interlayer conductor (conductor 4a) located on the second surface and coupling the at least two first wiring conductors to each other (lead terminal 105 as shown in FIG. 5).
Regarding claim 2, Shibayama shows a semiconductor package ( FIG. 1) comprising, wherein the first interlayer conductor (conductor 4a) is a conductor for a low-frequency alternating current signal or a direct current signal (underlined limitations considered as product by process).
Regarding claim 3, Shibayama shows a semiconductor package ( FIG. 1) comprising, wherein the first interlayer conductor is a grounding conductor (base plate can be used as ground terminal).
Regarding claim 4, Shibayama shows a semiconductor package ( FIG. 1) comprising, wherein the wiring laminate portion ( element 3) comprises two first interlayer conductors (element 4) extending side by side on the second surface (see FIG. 2).
Regarding claim 5, Shibayama shows a semiconductor package ( FIG. 1) comprising, wherein the wiring laminate portion comprises a recess (wind 5) located in the second surface, and the first interlayer conductor is located in the recess (see FIG. 2).
Regarding claim 12, Shibayama shows a semiconductor package ( FIG. 1) comprising, wherein semiconductor package according to any one and an electronic component ([0033]) located on the first surface.
Allowable Subject Matter
Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893