Prosecution Insights
Last updated: May 29, 2026
Application No. 18/557,843

METHOD FOR TRIMMING THE LIGHT SENSITIVITY OF A PHOTOTRANSISTOR

Non-Final OA §102
Filed
Oct 27, 2023
Priority
Apr 28, 2021 — DE 10 2021 110 886.1 +1 more
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
VISHAY SEMICONDUCTOR GMBH
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 838 resolved
+16.6% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
46.9%
+6.9% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 15-16, 24-25 and 31-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aki et al. (Aki US 2003/0201433 of record). Regarding claims 15 and 30, Aki shows a method of trimming light sensitivity of phototransistors (phototransistor 200 in FIG. 9) that are produced in a wafer-based ( substrate 170) semiconductor process and that each have a rear-side collector ( N+ /22/30 collector in FIG. 9 and [0014]), a base (base 40 in FIG. 9 and [0014] embedded in the collector, an emitter ( emitter 50 in FIG. 9 and [0014]) embedded in the base, and a front- side metallization (electric lines 190) that comprises at least one bond pad (electrode 120) for the emitter (emitter 50), wherein regions of the front side covered by the metallization define a light-insensitive area (light emitting element 180) of the respective phototransistor (phototransistor 200) and metal-free regions of the front side define a light-sensitive area ( element 180) of the respective phototransistor ( phototransistor 200), wherein the method comprises the steps of measuring a collector-emitter current of the phototransistors ( the underlined limitations considered function of the phototransistor); and changing a size of the light-sensitive area by changing a size of the area covered by the metallization in dependence on the measured collector-emitter current ( the terms changing size and measured also considered function of the phototransistor of Aki). Regarding claim 16, Aki shows a method of trimming light sensitivity of phototransistors (phototransistor 200 in FIG. 9), wherein the front-side metallization comprises a trimming structure (structure 190 in FIG. 9), wherein changing the size of the light- sensitive area ( light emitting element 180) by changing the size of the area covered by the metallization comprises increasing the size of the light-sensitive area by changing the size of the area covered by the metallization ( structure 190) by removing at least a part of the trimming structure (interface between 190). Regarding claim 24, Aki shows a method of trimming light sensitivity of phototransistors (phototransistor 200 in FIG. 9), wherein the measurement of the collector-emitter current of the phototransistors (phototransistor 200)( comprises that the respective phototransistor is illuminated and the respective base (base 40) is unconnected or connected, or in that the measurement of the collector-emitter current of the phototransistors comprises that the respective base is connected and the respective phototransistor is unilluminated or illuminated (see FIG. 9). Regarding claim 25, Aki shows a method of trimming light sensitivity of phototransistors (phototransistor 200 in FIG. 9), wherein the metallization has as structures a bond pad for the emitter and a trimming structure and, optionally, additionally a bond pad for the base and/or at least one frame-like structure for shielding electrical fields, with the trimming structure being formed separately from the other structure or structures or being connected to the or at least one of the other structures (see FIG. 9). Regarding claims 31 and 35, Aki shows a phototransistor (phototransistor 200 in FIG. 9) that is produced in a wafer-based semiconductor ( substrate 170) process and whose light sensitivity ( element 180) can be trimmed and that has a rear-side collector (collector 22), a base (base 30) embedded in the collector (collector), an emitter (emitter 50) embedded in the base (base 30), and a front-side metallization (element 190) that comprises at least one bond pad (pad 120) for the emitter (emitter 50), wherein the regions of the front side covered by the metallization define a light-insensitive area ( element 180) of the phototransistor and the metal-free regions of the front side define a light-sensitive area of the phototransistor (phototransistor 200) , wherein the collector-emitter current can be measured, and wherein the size of the light-sensitive area can be changed in dependence on the measured collector-emitter current by changing the size of the area covered by the metallization (see FIG. 9). Regarding claim 32, Aki shows a phototransistor (phototransistor 200 in FIG. 9), wherein the front- side metallization comprises a trimming structure ( element 190), wherein changing the size of the light- sensitive area by changing the size of an area covered by the metallization comprises increasing the size of the light-sensitive area by changing the size of the area covered by the metallization by removing at least a part of the trimming structure (see FIG. 9). Regarding claim 33, Aki shows a phototransistor (phototransistor 200 in FIG. 9), wherein the phototransistor is configured for use in measuring an ambient light brightness (FIG. 9). Regarding claim 34, Aki shows a phototransistor (phototransistor 200 in FIG. 9), wherein the phototransistor is further configured for setting the brightness of an instrument panel lighting and/or of an interior lighting of a motor vehicle (FIG. 9). Allowable Subject Matter Claims 17-23 and 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 27, 2023
Application Filed
May 12, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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