DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Abstract
The abstract of the disclosure is objected to because there is lack of antecedent basis for “the base substrate.”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 2 discloses a limitation which is not supported by the drawings: “the first conductive layer is located between a first electrode of the light emitting element and the first semiconductor layer, and the second conductive layer is located between the first conductive layer and the first electrode of the light emitting element”.
No drawing explicitly illustrates this configuration. Therefore, the relative position of the first conductive layer, the first electrode of the light emitting element, and the second conductive layer must be shown or the feature canceled from the claim. No new matter should be entered.
The drawings are also objected to due to the following informalities:
Reference numbers are not legible in figures 1 and 2.
Numerous figures, including figures 5A, 5B, 15A, 15B, 21A, 21B, 31B, and 34 are not drawn with enough contrast to allow differentiation of all the labelled features.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities: “the data line which is closest to the first connection structure than the overlapping part” should be “the data line which is closer to the first connection structure than the overlapping part. “Appropriate correction is required.
Claim 11 is objected to because of the following informalities: “each of the two pixel circuit” should be “each of the two pixel circuits”. Appropriate correction is required.
Claim 18 is objected to because of the following informalities: Two limitations of claim 18, “a second electrode of the eighth transistor is connected with the gate electrode of the driving transistor and the first electrode plate of the storage capacitor;” and “the first electrode plate of the storage capacitor is connected with the gate electrode of the driving transistor and the second electrode of the eighth transistor”, disclose the same substance and are thus substantial duplicates. Also, another pair of limitations of claim 18, “the second electrode of the seventh transistor and the second electrode of the sixth transistor are connected with the first electrode of the light emitting element” and “a second electrode of the sixth transistor is connected with the first electrode of the light emitting element and a second electrode of the seventh transistor”, disclose the same substance and are thus substantial duplicates. Once instance in each of these two examples should be deleted.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18 recites “the third active part forms the third active part” (p.28, claim 18, lines 10 and 11). The examiner, noting that this same phrase is found in the specifications [0022], interprets this as a statement of identity (as a limitation cannot form itself), which by its nature does not disclose structure, and thus does not distinctly claim subject matter.
Claim 19 includes all the limitations of claim 18, therefore, it is rejected as above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 17, and 32 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. US 2022/0052140 A1, hereinafter “Choi.”
Regarding claim 1, Choi discloses a display substrate comprising:
a base substrate (figure 7, element 100)
and a pixel circuit, arranged on the base substrate and comprising a driving transistor and a storage capacitor. (Choi discloses a pixel circuit, comprising a base substrate and a pixel driving circuit [0011]. The pixel driving circuit includes a driving transistor and a capacitor [0005].)
wherein the display substrate further comprises a first conductive layer (figure 7, layer 121), a second conductive layer (123) and a first semiconductor layer (figure 7, D4)
the first conductive layer comprises a first connection structure (In Choi figure 7, the conductive layer 123 comprises connection structure 171.)
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the first connection structure (figure 7, 171) comprises a first end and a second end which are opposite to each other (The first connection structure (171) comprises a first end and a second end, as marked.)
the first end is connected with the first semiconductor layer (Figure 7 shows that connection structure 171 is connected to first semiconductor layer D4 by means of the first end of the connection structure, end 1)
and the second end (end 2) is electrically connected with a gate electrode (G1) of the driving transistor (T1 - [0096]) and a first electrode plate (figure 7, CE1) of the storage capacitor (Cst, see also figure 5),
the first conductive layer (figure 7, 121) is at a side of the first semiconductor layer (D4) away from the base substrate 100,
and the second conductive layer (figure 7, 123) is at a side of the first conductive layer away from the base substrate (100)
and an orthographic projection of the second conductive layer (figure 7, 123) on the base substrate overlaps with an orthographic projection of at least part of the first connection structure (171) on the base substrate (100), (as shown in figure 7).
Regarding claim 2, Choi discloses the display substrate according to claim 1, further comprising
a plurality of sub- pixels (See figure 3, where each pixel element comprises red, blue, and green subpixels [0085]),
wherein each of the plurality of sub-pixels comprises the pixel circuit and a light emitting element (Paragraph [0076] describes the plurality of red, green, or blue light emitting pixels as comprising a pixel circuit and an organic light-emitting diode),
the first conductive layer (figure 7, 121) is located between a first electrode of the light emitting element (210) and the first semiconductor layer (D4),
and the second conductive layer (figure 7, 123) is located between the first conductive layer (121) and the first electrode of the light emitting element (210).
Regarding claim 17, Choi discloses the display substrate according to claim 2, wherein
the second conductive layer (figure 7, 123) comprises a data line (DL) and a first power signal line (PL2),
and an orthographic projection of the first power signal line on the base substrate covers more than 50% of an orthographic projection of the first connection structure on the base substrate. (Annotated Choi figure 7 below illustrates that the orthographic projection, indicated by the labeled shadow of the first power signal line (P2) on the base substate (100), overlaps by more than 50% the projection of the first connection structure (103) on the base substrate, indicated by the labeled shadow of the first connection structure on the base substrate. As easily seen, the region of overlap of the orthographic projections of these structures, indicated in figure 7, is larger than the region of no overlap.)
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Regarding claim 32, Choi discloses a display device comprising the display substrate of claim 1 (see rejection of claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 18 is rejected as being unpatentable over Choi et al. US 2022/0052140 A1 in view of, Ma et al. US 2021/0294382 A1 (hereinafter Ma).
Regarding claim 18, Choi discloses the display substrate according to claim 1, wherein,
the pixel circuit further comprises a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor; (In figure 5, Choi discloses a pixel circuit comprising six transistors (T2, T3, T4, T5, T6, and T7 in addition to the drive transistor (T1) disclosed in claim 1.)
a gate electrode of the first transistor (T4) is connected with a reset control signal line (SL3),
a first electrode of the first transistor (T4) is connected with a first initial signal line (Vint1),
a gate electrode of the second transistor (T3) is connected with a first scanning signal line (SL4),
and a second electrode of the second transistor (T3) is connected with a second electrode of the driving transistor (T1) and a first electrode of the sixth transistor (T6);
a first electrode of the driving transistor (T1) is connected with a second electrode of the fourth transistor (T2) and a second electrode of the fifth transistor (T5),
and the second electrode of the driving transistor (T1) is connected with the second electrode of the second transistor (T3) and the first electrode of the sixth transistor (T6);
a first electrode of the fourth transistor (T2) is connected with the data line (DL),
and a second electrode of the fourth transistor (T2) is connected with the first electrode of the driving transistor (T1) and the second electrode of the fifth transistor (T5);
a gate electrode of the fifth transistor (T5) is connected with a first light emission control signal line (EL),
a first electrode of the fifth transistor (T5) is connected with a first power signal line (PL) and a second electrode plate of the storage capacitor (CE2),
and a second electrode of the fifth transistor (T5) is connected with the second electrode of the fourth transistor (T2) and the first electrode of the driving transistor (T1);
a gate electrode of the sixth transistor (T6) is connected with the first light emission control signal line (EL),
a first electrode of the sixth transistor (T6) is connected with the second electrode of the driving transistor (T1) and the second electrode of the second transistor (T3),
and a second electrode of the sixth transistor (T6) is connected with the first electrode of the light emitting element (OLED) and a second electrode of the seventh transistor (T7);
a first electrode of the seventh transistor (T7) is connected with a second initial signal line (Vint2),
and the second electrode of the seventh transistor (T7) and the second electrode of the sixth transistor (T6) are connected with the first electrode of the light emitting element (OLED);
and a second electrode of the eighth transistor (T4) is connected with the gate electrode of the driving transistor (T1) and the first electrode plate of the storage capacitor (CE1);
the first electrode plate of the storage capacitor (Ce1) is connected with the gate electrode of the driving transistor (T1) and the second electrode of the eighth transistor (T4),
and the second electrode plate of the storage capacitor (CE2) is connected with the first power signal line (PL).
Choi is silent regarding:
an eighth transistor
a second electrode of the first transistor is connected with a first electrode of the eighth transistor and a first electrode of the second transistor;
a gate electrode of the fourth transistor is connected with the first scanning signal line,
a gate electrode of the driving transistor is connected with a second electrode of the eighth transistor and a first electrode plate of the storage capacitor (CE1),
a gate electrode of the seventh transistor is connected with the first scanning signal line or the reset control signal line,
a gate electrode of the eighth transistor is connected with a second scanning signal line (SL1/SL2),
a first electrode of the eighth transistor is connected with the second electrode of the first transistor (T4) and the first electrode of the second transistor (T2),
However, Ma discloses a pixel driving circuit for a display device (figure 13) that comprises:
an eighth transistor (figure 13, T4)
a second electrode of the first transistor (T5) is connected with a first electrode of the eighth transistor (T4) and a first electrode of the second transistor (T8);
a gate electrode of the fourth transistor (T5) is connected with the first scanning signal line (S1),
a gate electrode of the driving transistor (T3) is connected with a second electrode of the eighth transistor (T4) and a first electrode plate of the storage capacitor (C1),
a gate electrode of the seventh transistor (T9) is connected with the first scanning signal line (S1) or the reset control signal line,
a gate electrode of the eighth transistor (T4) is connected with a second scanning signal line (S2),
a first electrode of the eighth transistor (T4) is connected with the second electrode of the first transistor (T5) and the first electrode of the second transistor (T8),
Ma’s modifications, referenced above, to the seven-transistor pixel-driving circuit disclosed by Choi, include adding an eight transistor and changing Choi’s configuration of scan lines. According to Ma, these changes stabilize the display (Ma [0055-0056]) and increase light transmission (Ma [0060]). Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to incorporate the additional transistor and other modifications of Ma referenced above to the pixel-driving circuit disclosed by Choi in order to improve the luminescence and stability of the display device.
Allowable Subject Matter
Claims 3-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art does not teach or render obvious the display substrate according to claim 2, wherein the second conductive layer comprises a data line, a first electrode transfer line and a first power signal line which are spaced apart from each other, the first electrode transfer line is connected with the first electrode of the light emitting element, and an orthographic projection of the first electrode transfer line on the base substrate overlaps with an orthographic projection of a part of the first connection structure on the base substrate in the combination as claimed.
Claims 4-16 further limit claim 3 and would be considered allowable if claim 3 was written in independent form.
Regarding claim 19, the prior art does not teach or render obvious the display substrate according to claim 18, further comprising: a first active layer, between the base substrate and the second conductive layer, wherein the first active layer comprises a first active part, a second active part, a third active part, a fourth active part, a fifth active part, a sixth active part and a seventh active part, the first active part forms a channel region of the first transistor, the second active part forms a channel region of the second transistor and the third active part forms the third active part, the fourth active part forms a channel region of the fourth transistor, the fifth active part forms a channel region of the fifth transistor, the sixth active part forms a channel region of the sixth transistor, and the seventh active part forms a channel region of the seventh transistor; a second active layer, between the first active layer and the second conductive layer, wherein the second active layer comprises an eighth active part, the eighth active part forms a channel region of the eighth transistor in the combination as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 11,373,599 B1, US 2021/0151540 A1, US 2020/0286972, Luo, H., et al. (2020), 24-3: Complementary LTPO Technology, Pixel Circuits and Integrated Gate Drivers for AMOLED Displays Supporting Variable Refresh Rates. SID Symposium Digest of Technical Papers, 51: 351-354 (All show similar display substrate and/or similar pixel-driving circuits).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Thu. 7 am- 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818