DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16, 17 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimada et al US 2004/0065913.
Pertaining to claim 16, Shimada teaches a three-dimensional memory comprising:
a substrate 40 lying in a plane, wherein the plane extends in a first direction and a second direction; and
a storage array layer 41 comprising:
at least one storage structure comprising N capacitors 20 disposed side by side on the substrate, wherein each of the N capacitors 20 comprises:
a first electrode 21;
a first dielectric layer 22; and
a second electrode 23,
wherein the first electrode, the first dielectric layer, and the second electrode are sequentially stacked on the substrate in a third direction away from the substrate see Figure 4,
wherein N>2 Figure 4 shows multiple capacitors 20, and
wherein N is an integer There is a whole number of capacitors, no fractional capacitors.
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Pertaining to claim 17, Shimada teaches the three-dimensional memory of claim 16, further comprising:
M storage array layers 41/42 stacked in the third direction and perpendicular to the substrate, wherein M>2 [0078] teaches more than 2, and wherein M is an integer (not fractional); and
a second dielectric layer 35 located between two adjacent storage array layers 41/41 of the M storage array layers.
Pertaining to claim 27, Shimada teaches the three-dimensional memory of claim 16, wherein the storage array layer 41 comprises a plurality of storage structures arranged in an array (a “storage structure” can be a grouping of capacitors as illustrated in Figure 4 marked up below).
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Pertaining to claim 28, Shimada teaches a chip package structure comprising:
a package substrate 10; and
a three-dimensional memory [0040] disposed on the package substrate and comprising:
a substrate 40 lying in a plane, wherein the plane extends in a first direction and a second direction; and
a storage array layer 41 comprising:
at least one storage structure comprising N capacitors 20 disposed side by side on the substrate, wherein each of the N capacitors 20 comprises:
a first electrode 21;
a first dielectric layer 22; and
a second electrode 23,
wherein the first electrode, the first dielectric layer, and the second electrode are sequentially stacked on the substrate in a third direction away from the substrate see Figure 4,
wherein N>2 Figure 4 shows multiple capacitors 20, and
wherein N is an integer There is a whole number of capacitors, no fractional capacitors.
Pertaining to claim 29, Shimada teaches the chip package structure of claim 28, further comprising a control chip 40 elements 15, wherein the control chip is disposed on the package substrate and is located on a same plane as the three-dimensional memory, or wherein the control chip and the three-dimensional memory are stacked on the package substrate element 40 includes elements 15 (selective transistors) which can be considered a “control chip” [0046] as they control access to the capacitor array.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 30 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al US 2004/0065913 and further in view of Bernhardt et al US 2017/0186815.
Pertaining to claim 30, Shimada teaches a chip package structure Figure 4 comprising:
a package substrate 10; and
a three-dimensional memory [0040] disposed on the package substrate and comprising:
a substrate 40 lying in a plane, wherein the plane extends in a first direction and a second direction; and
a storage array layer 41 comprising:
at least one storage structure comprising N capacitors 20 disposed side by side on the substrate, wherein each of the N capacitors 20 comprises:
a first electrode 21;
a first dielectric layer 22; and
a second electrode 23,
wherein the first electrode, the first dielectric layer, and the second electrode are sequentially stacked on the substrate in a third direction away from the substrate see Figure 4,
wherein N>2 Figure 4 shows multiple capacitors 20, and
wherein N is an integer There is a whole number of capacitors, no fractional capacitors.
Shimada fails to teach wherein the chip package structure is mounted onto a mainboard. Bernhardt teaches a memory device that includes 3D memory [0002], wherein the package substrate is mounted to a mainboard 122 [0027]. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teaching of Shimada with that of Bernhardt by mounting the package of Shimada to a mainboard. The ordinary artisan would have looked to do this for the purpose of incorporating the memory components into a finished product such as a computer or other end user electronic device that requires memory.
Pertaining to claim 35, Shimada teaches the three-dimensional memory of claim 30, further comprising:
M storage array layers 41/42 stacked in the third direction and perpendicular to the substrate, wherein M>2 [0078] teaches more than 2, and wherein M is an integer (not fractional); and
a second dielectric layer 35 located between two adjacent storage array layers 41/41 of the M storage array layers.
Claim(s) 18, 19, 31 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimada et al US 2004/0065913 and further in view of Tran et al US 10,978,553
Pertaining to claims 18 and 31, Shimada teaches the three-dimensional memory of claims 16 and 30, but fails to teach the specific structure for the capacitor. Tran teaches a capacitor 611-1, wherein the first electrode 636 comprises:
a first surface located away from the substrate 601; and
at least one first side surface See Figure 6 marked up below,
wherein the first dielectric layer 623 is configured to cover the first surface and the at least one first side surface See Figure 6 and comprises:
a second surface located away from the substrate; and
at least one second side surface,
wherein the second electrode 625 is configured to cover the second surface and the at least one second side surface See Figure 6, and
wherein second electrodes of two adjacent capacitors of the N capacitors 611-1 / 611-2 are disposed at an interval See Figure 6.
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Tran into the device of Shimada by using the vertical capacitor design of Tran. The ordinary artisan would have been motivated to modify Shimada in the manner set forth above for at least the purpose of increasing the capacitance of each cell of the memory device as the vertical capacitor design has a small footprint, see Tran Col 2 lines 4-10.
Pertaining to claims 19 and 32, Shimada in view of Tran teaches the three-dimensional memory of claims 18 and 31, wherein first dielectric layers 623 of the N capacitors 611-1 / 611-2 are configured to define a connected integrated structure (It is not clear if “connected integrated structure” means that the N capacitors are connected together continuously with layer 623, or if layer 623 defines a connected integrated structure ie that each capacitor itself is multiple components integrated together) See Figure 6 of Tran marked up below.
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Pertaining to claims 20 and 33, Shimada in view of Tran teaches the three-dimensional memory of claims 18 and 31, where in the N capacitors are disposed side by side in the second direction, wherein the first electrode 636 comprises a first cross section having a trapezoid shape (a rectangle is a trapezoid, and “a first cross section” can be arbitrarily selected), parallel to the second direction, and perpendicular to the substrate. See Figure 6 of Tran marked up below
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Allowable Subject Matter
Claims 21-26 and 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claims 21 and 34, the prior art does not teach nor suggest alone or in combination wherein the at least one storage structure further comprises: N gating transistors comprising gates and third electrodes, wherein a fourth electrode of one gating transistor of the N gating transistors is electrically coupled to the first electrode of one capacitor of the N capacitors, a word line electrically coupled to the gates and a bit line electrically coupled to the third electrodes
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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