Prosecution Insights
Last updated: April 19, 2026
Application No. 18/558,091

DISPLAY SUBSTRATE AND DISPLAY DEVICE

Non-Final OA §102§103§112
Filed
Oct 30, 2023
Examiner
WALJESKI-MOSES, KATRINA MARIE HESTER
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
1 granted / 1 resolved
+32.0% vs TC avg
Strong +100% interview lift
Without
With
+100.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
7 currently pending
Career history
8
Total Applications
across all art units

Statute-Specific Performance

§103
53.6%
+13.6% vs TC avg
§102
32.1%
-7.9% vs TC avg
§112
14.3%
-25.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement s (IDS) submitted on April 23, 2024 and on March 4, 2025 w ere filed after the mailing date of the application on October 30, 2023 . The submission s are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement s are being considered by the examiner. Drawings The drawings are objected to due to lack of contrast and clarity . All drawings that illustra te superposition of layers (including, but not limited to figures 1, 2, 5B, 15b, 21b , 31b ) are difficult to read , as there is not enough contrast to discern all the labeled elements. Other figures, for example figure 9 are difficult to read due to the size of the regions indicated. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 8 is objected to because of the following informalities: lack of antecedent basis for “ the first electrode transfer line . ” T his claim should be dependent on claim 7 to correct this. Appropriate correction is required. Claim 12 is objected to because of the following informalities: lack of antecedent basis for “ the strip-shaped part,” “ the block-shaped part,” and “the second direction .” T his claim should be dependent on claim 9 to correct this . Appropriate correction is required. Claim 19 is objected to because of the following informalities: “ the plurality of sub-pixels comprise ” should be corrected to “ the plurality of sub-pixels comprises ” in two instances . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 teaches “ an entirety of the first connection structure is in a shape of a broken line extending away from the data line which is closest to the first connection structure ”. A “broken line” does not have a specific shape; therefore, this limitation does not particularly point out and distinctly claim a shape. A suggested alternate description that specifies the shape pictured in the figures is “ a line having a zigzag shape . ” Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 6 and 25 are rejected under 35 USC § 102 (a) (1) as being anticipated by Zhang et al . (CN 113707704B , cited in the IDS filed on April 23, 2024, see attached machine translation for specific citations described below ) Note: all he figures Regarding claim 1 , Zhang discloses a display substrate comprising: a base substrate ( figure 2, 001 ); a pixel circuit ( In figure 2 , which illustrates cross-section al structure of the display substrate of figure 5 , the element 102 shows the placement of the layer comprising this pixel circuit relative to the base substrate 001 - see the bottom of page 3 of the machine translation of Zheng ) on the base substrate . the pixel circuit comprising a storage capacitor comprising a first electrode plate and a second electrode plate which are opposite to each other ( see element 211 , capacitor in figure 2 , first electrode plate is the top plate of 211, the second electrode plate is the bottom plate ( see first full paragraph on page 7 of the machine translation ) , see also element C in figure 3, a schematic diagram of the pixel-driving circuit (description at the bottom of page 3 of the machine translation of Zheng ) ) ; wherein the display substrate further comprises a conductive film layer ( shown in figure 8 , which is a diagram showing the structure of a conductive layer of the display substrate illustrated in figure 5, described on page 4 of the machine translation of Zheng ), 4130040 960120 0 0 2766060 141605 0 0 the conductive film layer ( figure 8 ) comprises a first conductive part ( element 34 ); the first conductive part comprises a main part and a bridge part ( as shown on annotated figure 8 ), the main part corresponds to two second electrode plates (main 1 and main 2 are the plates) , and the bridge part connects the two second electrode plates ( see annotated figure 8 ), and the first conductive part comprises a notch between the two second electrode plates ( see the annotated figure 8 – main 1 and main 2 are the two second electrode plates ). Regarding claim 2, Zhang discloses the display substrate according to claim 1, wherein the pixel circuit further comprises a driving transistor ( I n figure 3 , a schematic representation of the pixel circuit , transistor T3 is the driving transistor.) ; the display substrate further comprises a first conductive layer ( figur es 8 and 12 , layer 4 ), a second conductive layer ( figure 10, layer 5 , described in the last paragraph on page 10 of the machine translation of Zheng ) and a first semiconductor layer ( figure 6a, layer 1 , also described in the last paragraph on page 10 of the machine translation of Zheng ), the first conductive layer comprises a first connection structure ( e lement 45 , of figure 12a and 12b , which are diagrams of one of the conductive layers of the display substrate of figure 5, described on page 4 of the machine translation of Zheng.) the first connection structure comprises a first end and a second end which are opposite to each other ( see figure 12b, element 45 has two ends ), the first end is connected with the first semiconductor layer ( figure 3, transistor T1 is part of the first semiconductor layer ) and the second end is electrically connected with a gate electrode (24) of the driving transistor ( figure 3, T3 ) and the first electrode plate of the storage capacitor ( figure 3, C ) (also see text description from Zhang ( from the machine translation , page 8 second full paragraph and page 15 first paragraph ) : “The control electrode of the driving transistor T3 is connected to the first node N1, that is, the control electrode of the driving transistor T3 is connected to the second plate of the storage capacitor C, the first electrode of the driving transistor T3 is connected to the second node N2, and the first electrode of the driving transistor T3 is connected ….. the first end of the third connecting portion 45 is connected to the control electrode of the driving transistor T3 through a via hole, and the second end is connected to the first area of the second transistor T2 through a via hole..”) ; the first conductive layer is located at a side of the first semiconductor layer away from the base substrate (See figure 18, where layer 4, the first conductive layer, which comprises elements 41, 45, and 421 , is located at a side of the first semiconductor layer, which comprises element 13, away from the base substrate layer 001.) the second conductive layer ( figure 1 8, layer 5 ) is located at a side of the first conductive layer away from the base substrate ( See figure 18, where one element of layer 5, element 532, is located at a side of the first conductive layer, comprising elements 45, 41, and 421, away from the base substrate, 001 .) and an orthographic projection of the second conductive layer ( figure 18, layer 5 ) on the base substrate ( 001 ) overlaps with an orthographic projection of at least part of the first connection structure ( 45 ) on the base substrate (See figure 18, where the orthographic projection of a part of the second conductive layer 532 overlaps an orthographic projection of at least part of the first connection structure 45 on the base substrate 001.) Regarding claim 3, Zhang discloses the display substrate according to claim 2, wherein an orthographic projection of the first conductive layer ( figure 15, layer 4 ) on the base substrate ( 001 ) does not overlap with an orthographic projection of the notch on the base substrate ( see figure 15 ), 3238500 1910715 0 0 -207645 1847215 0 0 and the orthographic projection of the second conductive layer ( figure 15, layer 5 ) on the base substrate does not overlap with the orthographic projection of the notch on the base substrate. ( See annotated figure 15 below – The notch area is here defined by the area of no overlap with layer 5, so therefore the orthographic projection of the second conductive layer (layer 5) does not overlap the orthographic projection of this notch. ) Regarding claim 4, Zhang discloses the display substrate according to claim 2, wherein an orthographic projection of the second electrode plate ( figure 7, element 24 ) on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate ( figure 8, element 34 - main 1 ) on the base substrate ( see figure 5 ). Regarding claim 5, Zhang discloses the display substrate according to claim 4, wherein the second electrode plate ( figure 8, 34 -main 1 ) is provided with an opening (341) , 2030730 2147570 0 0 an orthographic projection of a via hole ( Zhang machine translation page 15 first paragraph ) discloses “ the first end of the third connecting portion 45 is connected to the control electrode of the driving transistor T3 through a via hole ”) connected between the gate electrode of the driving transistor T3 ( Zhang (machine translation page 14 paragraph 6) also discloses: “ The first plate 24 can simultaneously serve as the control electrode (gate) of the driving transistor T3 ” ) and the first connection structure 45 on the base substrate overlaps with an orthographic projection of the opening 341 on the base substrate 001 , ( See annotated figure 11 ) and a conductive structure in the via hole is insulated ( by insulating layer 74) from the second electrode plate 34 – main 1 . (see fig ure 18 ) Regarding claim 6, Zhang discloses t he display substrate according to claim 2, further comprising a plurality of sub-pixels ( Zhang – Summary of Invention section ) , wherein each of the sub-pixels comprises the pixel circuit and a light emitting element ( Zhang – Summary of Invention section ) , the first conductive layer ( layer 4 , comprising 421, 41, 45 ) is located between a first electrode of the light emitting element 611 ( F igure 16 shows that 611 lies in layer 6, as does element 612 . ) and the first semiconductor layer ( layer 1, comprising 13 ) , ( Figure 18 shows that layer 4 , comprising 41, 45, and 421, is above the first semiconductor layer , which comprises element 13 . Figure 18 also shows that layer 4, is below layer 6 comprising 612a and the first electrode of the light emitting element 611 . Therefore, layer 4 is located between layers 6 and 1. ), and the second conductive layer ( layer 5 ) is located between the first conductive layer ( layer 4 ) and the first electrode of the light emitting element ( 611 ) ( Figure 17 shows that layer 5 is between layer 6 (shown by 612b) and layer 4 (shown by 46) ). Regarding claim 25, Zheng discloses a display device comprising the display substrate according to claim 1. ( see rejection of claim 1 and title of Zheng ) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 7 , 13, and 19 are rejected under 35 U.S.C. 103 as being obvious over Zhang in view of Li et al . ( WO2022082596A1 , cited in IDS filed on March 4, 2025, where Li et al . US 12,048,216 B2 is used as a translation ) . Regarding claim 7, Zhang discloses the display substrate according to claim 6, wherein the second conductive layer ( figure 10, layer 5 ) comprises a data line ( 51 ) and a first power signal line ( 52 ) which are spaced apart from each other ( see figure 10 ) . Zhang lacks : a first electrode transfer line , (spaced from the data line and power signal line) the first electrode transfer line is connected with the first electrode of the light emitting element and an orthographic projection of the first electrode transfer line on the base substrate overlaps with an orthographic projection of a part of the first connection structure on the base substrate . However, Li discloses a first electrode transfer line ( figure 8, IPB1, which is space from the data line (figure 8, DL_OO) and the power line (Vdd1) as shown in figure 8) , the first electrode transfer line (IPB 1) is connected with the first electrode of the light emitting element ( as described in [0051], IPB1 is electrically connected to an electrode of the first light emitting element ) and an orthographic projection of the first electrode transfer line on the base substrate overlaps with an orthographic projection of a part of the first connection structure on the base substrate ( As shown in figure 9, the orthographic projection of the IPB1 on the base substrate BS is at least partially overlapping with an orthographic projection of the connecting structure C11 on the base substrate BS .) Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing to add the electrode transfer line as described by Li to the similar display device of Zhang in order to prevent signal interference within the pixel driving circuit, as described by Li in paragraph [0053]. Regarding claim 13 , Zhang as modified by Li discloses t he display substrate according to claim 7 , wherein the second electrode plate and the first power signal line are electrically connected ( Zhang second electrode plate 34 -main1 is electrically connected to first power signal line VDD, as shown in figure 3 ) . Regarding claim 19, Zheng as modified by Li discloses the display substrate according to claim 7 , wherein the plurality of sub-pixels comprise s a plurality of first sub-pixels (P1 or R ) , a plurality of second sub-pixels (P 3 or G ) and a plurality of third sub-pixels (P 2 or B ) ( See figures 1a, 1b, and 15 of Zheng ) ; two second sub-pixels (P2 or G ) form a second sub-pixel pair (pair of G - G) , the two second sub-pixels in one second sub-pixel pair are a first pixel block (G) and a second pixel block (G) respectively, and the first pixel block (G) and the second pixel block (G) are alternately arranged along the first direction or the second direction ( see Zheng figures 1a and 1b) ; the plurality of sub-pixels comprise s a plurality of minimum repeating units, and one minimum repeating unit comprises one first sub-pixel (R) , one first pixel block (G) , one second pixel block (G) and one third sub-pixel (B) . ( See figures 1a, 1b, and 15 of Zheng ) Allowable Subject Matter Claims 9-11 , 12, and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 9, the prior art does not teach nor render obvious the display substrate according to claim 7, wherein, the extending direction of the data line is a first direction, and a direction perpendicular or substantially perpendicular to the extending direction of the data line is a second direction; the first conductive layer further comprises a power signal connection line, the power signal connection line comprises a main part and a branch part, an extending direction of an entirety of the power signal connection line is parallel to the second direction, and an extending direction of the branch part is parallel to the first direction; the first power signal line comprises a block-shaped part and a strip-shaped part extending along the first direction as a whole, the strip-shaped part connects adjacent block-shaped parts, and the main part of the power signal connection line is connected with the first power signal line to form a grid shape in the combination as claimed. Claims 10 and 11 further limit claim 9 and would be considered allowable if claim 9 were written in independent form. Regarding claim 12, the prior art does not teach or render obvious a display substrate according to claim 8 ( correct to 9 , as described in the claim objection section above ), wherein a width of the block-shaped part in the second direction is greater than a width of an entirety of the strip-shaped part in the second direction in the combination as claimed. Regarding claim 14 , the prior art does not teach nor render obvious the display substrate according to claim 7, wherein the pixel circuit further comprises a first transistor, a second transistor, a sixth transistor and a seventh transistor; a first electrode of the first transistor is connected with the gate electrode of the driving transistor, a second electrode of the first transistor is connected with a first initial signal line, a first electrode of the second transistor is connected with the gate electrode of the driving transistor, a second electrode of the second transistor is connected with a second electrode of the driving transistor, a first electrode of the sixth transistor is connected with the second electrode of the driving transistor, and a first electrode of the seventh transistor is connected with the second electrode of the sixth transistor, a second electrode of the seventh transistor is connected with a second initial signal line; the display substrate further comprises: a first active layer between the base substrate and the second conductive layer, wherein the first active layer comprises a third active part configured to form a channel region of the driving transistor, a sixth active part configured to form a channel region of the sixth transistor, and a seventh active part configured to form a channel region of the seventh transistor; a second active layer between the first active layer and the second conductive layer, wherein the second active layer comprises a first active part configured to form a channel region of the first transistor and a second active part connected with the first active part and configured to form a channel region of the second transistor in the combination as claimed. Claims 15-18 further limit claim 14 and would be considered allowable if claim 9 w as written in independent form. Note - no prior art rejection was made for claim 8 only a 35 U.S.C. 112b rejection as seen above. Upon overcoming the 35 U.S.C. 112b rejection this claim would likely be considered objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record but not relied upon that is considered pertinent to the applicant’s disclosure: US-20200286972-A1 , US-20210151540-A1 , US-11373599-B1 , CN-114093898-A , and US-20200193909-A1 , which all disclose similar OLED display substrates and devices . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KATRINA M H WALJESKI-MOSES whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0731 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon- Fri 7:30 am- 3:30 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jeff Natalini can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-2266 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KATRINA WALJESKI-MOSES/ Examiner, Art Unit 2818 /JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Oct 30, 2023
Application Filed
Mar 26, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+100.0%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allow rate.

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