Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Response to Arguments
Applicant's arguments filed 8/10/2026 have been fully considered but they are not persuasive. Applicant argues that Chen does not disclose the claimed group-level layer arrangement because “each individual set in Chen is inherently a cross-layered mixed structure,” and further argues that Chen lacks the claimed overlap because there is “no group-to-group overlap of connecting-line projections.”
However, under BRI, the claim language recites that an orthographic projection of the first connecting lines “at least partially overlaps” an orthographic projection of the second connecting lines, placing no limitation on the continuous length or directional axis of the overlap. Chen’s physical trace crossover between different conductor layers inherently creates a point intersection on the substrate, which directly meets the structural limitation of at least partially overlapping in orthographic projection.
To the extent the Applicant contends Chen’s sets are cross=layer mixed structures rather than strict group-by-layer isolated sets, it would have been obvious to a person having ordinary skill in the art at the time of the invention to consolidate the first line groups on a first layer and the second line groups on a second layer as a routine design choice to simplify mask layout and achieve compact multi-layer routing in the peripheral area as suggested by Chen.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Chen et al. (US 20140139255 A1)
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CLAIM 1: Chen teaches a display panel, comprising a display area and a first non-display area located on one side of the display area [Chen FIG. 1, display area 110 and peripheral area 120], the display panel further comprising: a substrate [Chen Abstract: "A display panel includes a first substrate”];
a plurality of gate scan lines CA/GA disposed on the substrate and located in the display area 110, wherein each of the gate scan lines extends along a first direction (vertical), and the gate scan lines are arranged at intervals along a second direction (horizontal ) [Chen Fig. 1 & ¶211: "pixel control lines CA... configured in the display area 110... "];
a plurality of first line groups S1 [S11+S12] disposed on the substrate and located in the first non-display area 120, wherein each of the first line groups comprises at least two gate lines extending along the first direction first direction and a plurality of first connecting lines, each of the gate lines is electrically connected to a corresponding one of the gate scan lines, and every two adjacent gate lines exhibit a voltage difference in each of the first line groups exhibit a voltage difference; wherein in the same first line group, each of the first connecting lines is electrically connected to a corresponding one of the gate lines [Chen ¶21-24: Describe a test methodology utilizing at least two sub-signal lines (\(S_{11}, S_{21}\)) driven by distinct test signals (\(F_1, F_2\)) to create a functional voltage difference for distinguishing short circuits. This differentiation is methodological rather than structural because Chen teaches that the voltage levels and relationships (and consequently the difference) are selectable based on the required testing result, rather than being inherently fixed by the physical architecture. Furthermore, because the gate scan lines receive independent signals during normal operation, the claimed ‘functional difference’ is inherently achieved by the described structure during operation.]; and
a plurality of second line groups disposed on the substrate and located in the first non-display area, wherein each of the second line groups comprises at least two gate lines extending along the first direction and a plurality of second connecting lines, each of the gate lines is electrically connected to a corresponding one of the gate scan lines, and every two adjacent gate lines in each of the second line groups exhibit a voltage difference [Chen - Fig. 1 & ¶22: "second sets S2... of sub-signal lines... S12 and S22"]; wherein in the same second line group, each of the second connecting lines is electrically connected to a corresponding one of the gate lines;
wherein the first line groups and the second line groups are located in different layers [Chen - Fig. 2 ]; and
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an orthographic projection of the gate lines in the second line groups projected on the substrate is alternately arranged with an orthographic projection of the gate lines in the first line groups projected on the substrate [Chen FIG. 2 shows sequence S11, S12, S21, S22 alternating between layers]; and
wherein the plurality of first connecting lines and the plurality of second connecting lines are formed in different metal layers, and an orthographic projection of the first connecting lines on the substrate at least partially overlaps an orthographic projection of the second connecting lines on the substrate (Chen Fig. 1. Shows connecting lines in different layers crossing over one another. While crossing over may not be significantly “overlapping” a long a line in a common direction. Broadest reasonable interpretation (BRI), a physical crossover point non the less creates a finite region of orthographic projection overlap. To the extent the crossover is not viewed aa a full line-on-line overlap, it would have been obvious to a PHOSITA at the time of the invention to form connecting lines in different metal layers that overlap in orthographic projection, as Chen explicitly suggests using different layers for signal lines to achieve compact multi-layer routing in the peripheral non-display area.).
CLAIM 2: Chen teaches the display panel according to claim 1, wherein in the same first line group, every two adjacent connecting lines exhibit a voltage difference [Chen FIG 1 & ¶31- signals F1/F2];
in the same second line group, every two adjacent connecting lines exhibit a voltage difference [Chen FIG 1 & ¶31- signals F1/F2]; and
each of the first connecting lines is connected to an end portion of a corresponding one of the gate lines that is away from the display area, and each of the second connecting lines is connected to an end portion of a corresponding one of the gate lines that is away from the display area [Chen FIGs. 1 & 2: show lines S11 and S12 are routed closely in different layers; gate line end points are connected connecting lines; overlapping in the non-display area 120 of FIG 1.]
CLAIM 3: Chen teaches the display panel according to claim 2, wherein a number of the gate lines in the first line group is equal to a number of the gate lines in the second line group [Chen FIG 1], and a voltage on each gate line in the first line group is equal to a voltage on the corresponding gate line in the second line group [Chen ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1 and D2. A functional states (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 4: Chen teaches the display panel according to claim 3, wherein each of the first line groups comprises a first gate line and a second gate line arranged adjacent to each other, and each of the second line groups comprises a third gate line and a fourth gate line arranged adjacent to each other, wherein a voltage on the first gate line is equal to a voltage on the third gate line, and a voltage on the second gate line is equal to a voltage on the fourth gate line [Chen FIGs 1-2 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1 and D2. A functional states (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 5: Chen teaches the display panel according to claim 2, further comprising a plurality of third line groups and a plurality of fourth line groups arranged in a same layer as the first line groups [Chen ¶36: may include third sets S4 and fourth sets S5], wherein one of the third line groups and one of the fourth line groups are disposed between every two adjacent ones of the first line groups, each of the third line groups and the fourth line groups comprises at least two gate lines, every adjacent pair of the gate lines in the third line groups exhibit a voltage difference, and every adjacent pair of the gate lines in the fourth line groups exhibit a voltage difference [Chen Fig. 1], wherein a voltage on at least one gate line in the third line group is different from a voltage on the gate line in the first line group [Chen Paragraph [0028]: "test signal F1 and second test signal F2 are different"], and in the first line group and the third line group arranged adjacently, the gate line in the third line group close to the first line group has a voltage difference from the gate line in the first line group close to the third line group [Chen ¶28]; a voltage on at least one gate line in the fourth line group is different from the voltage on the gate line in the first line group, and in the first line group and the fourth line group arranged adjacently, the gate line in the fourth line group close to the first line group has a voltage difference from the gate line in the first line group close to the fourth line group [Chen ¶28]; and in the third line group and the fourth line group arranged adjacently, the gate line in the third line group close to the fourth line group has a voltage difference from the gate line in the fourth line group close to the third line group [Chen FIGs 1-2 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 6: Chen teaches the teaches the display panel according to claim 5, wherein each of the first line groups comprises a first gate line and a second gate line arranged adjacently; each of the third line groups comprises a fifth gate line and a first gate line, and the fifth gate line and the second gate line exhibit a voltage difference; in the first line group and the third line group arranged adjacently, the fifth gate line is close to the first line group [Chen FIGs 1-2 & 8 - ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].each of the fourth line groups comprises a sixth gate line and the second gate line arranged adjacently, the sixth gate line and the first gate line exhibit a voltage difference, and in the first line group and the fourth line group arranged adjacently, the second gate line is close to the first line group [Chen FIGs 1-2 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 7: Chen teaches the display panel according to claim 6, wherein a voltage on the fifth gate line is equal to a voltage on the sixth gate line [Chen FIGs 1-2 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional states (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 8: Chen teaches the display panel according to claim 1, further comprising a second non-display area located on another side of the display area, wherein the second non-display area is arranged opposite to the first non-display area and provided with the first line groups and the second line groups, and wherein the first line groups and the second line groups in the first non-display area are electrically connected to odd-numbered ones of the gate scan lines, and the first line groups and the second line groups in the second non-display area are electrically connected to even-numbered ones of the gate scan lines [Chen FIG. 1 & ¶21: peripheral device 120 surrounds the display area 110. Fig. 8 shows lines 40 and 50 on different sides fo the display area.].
Claim 9: Chen teaches the display panel according to claim 1, further comprising a second non-display area located on another side of the display area, wherein the second non-display area is arranged opposite to the first non-display area and provided with the first line groups and the second line groups, and wherein the first line groups in the first non-display area are symmetrically arranged with the first line groups in the second non-display area, and the second line groups in the first non-display area are symmetrically arranged with the second line groups in the second non-display area [Chen FIG. 1: depicts symmetrical peripheral areas on opposite sides of the display area].
Claim 10: Chen teaches the display panel according to claim 1, wherein the first line groups or the second line groups are arranged in a same layer as the gate scan lines [Chen ¶22: first sub-signal lines S11 are formed on the first metal layer M1, where M1 is the standard layer for gate lines GA].
Claim 11: Chen teaches an electronic device, comprising a display panel, wherein the display panel comprises a display area and a non-display area located on one side of the display area, the display panel further comprises:
a substrate [Chen ¶21: first substrate 20];
a plurality of gate scan lines disposed on the substrate and located in the display area, wherein each of the gate scan lines extends along a first direction, and the gate scan lines are arranged at intervals along a second direction [Chen ¶21: gate lines GA];
a plurality of first line groups disposed on the substrate and located in the first non-display area, wherein each of the first line groups comprises at least two gate lines extending along the first direction and a plurality of first connecting lines, each of the gate lines is electrically connected to a corresponding one of the gate scan lines, and every two adjacent gate lines in each of the first line groups exhibit a voltage difference; wherein in the same first line group, each of the first connecting lines is electrically connected to a corresponding one of the gate lines [Chen Fig. 1 -- ¶22: First sets of sub-signal lines S1; ¶28: Different test signals F1, F2 establish capability of functional voltage differences or equalities]; and
a plurality of second line groups disposed on the substrate and located in the first non-display area, wherein each of the second line groups comprises at least two gate lines extending along the first direction, each of the gate lines is electrically connected to a corresponding one of the gate scan lines, and every two adjacent gate lines exhibit a voltage difference [Chen ¶22: Second sets of sub-signal lines S2];
a plurality of second line groups disposed on the substrate and located in the first non-display area, wherein each of the second line groups comprises at least two gate lines extending along the first direction and a plurality of second connecting lines, each of the gate lines is electrically connected to a corresponding one of the gate scan lines, and every two adjacent gate lines in each of the second line groups exhibit a voltage difference [Chen FIGS 1 & 2 - ¶22: S11 on layer M1, M2. FIG 2 shows alternating layout. Overlapping connecting segments is shown in non-display region 120 and understood from lines being formed in different levels.];
wherein in the same second line group, each of the second connecting lines T1 is electrically connected to a corresponding one of the gate lines S11/S12 (Chen Fig. 1)
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Claim 12: Chen teaches the electronic device according to claim 11, wherein in the same first line group, every two adjacent connecting lines exhibit a voltage difference;
in the same second line group, every two adjacent connecting lines exhibit a voltage difference; and
each of the first connecting lines is connected to an end portion of a corresponding one of the gate lines that is away from the display area, and each of the second connecting lines is connected to an end portion of a corresponding one of the gate lines that is away from the display area [Chen FIGS 1 & 2 - ¶22: S11 on layer M1, M2. FIG 2 shows alternating layout. Overlapping connecting segments is shown in non-display region 120 and understood from lines being formed in different levels.].
Claim 13: Chen teaches the electronic device according to claim 12, wherein a number of the gate lines in the first line group is equal to a number of the gate lines in the second line group, and a voltage on each gate line in the first line group is equal to a voltage on the corresponding gate line in the second line group [Chen FIG 1 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1 and D2. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 14: Chen teaches the electronic device according to claim 13, wherein each of the first line groups comprises a first gate line and a second gate line arranged adjacent to each other, and each of the second line groups comprises a third gate line and a fourth gate line arranged adjacent to each other, wherein a voltage on the first gate line is equal to a voltage on the third gate line, and a voltage on the second gate line is equal to a voltage on the fourth gate line [Chen FIGs 1-2 & ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1 and D2. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 15: Chen teaches the electronic device according to claim 12, wherein the display panel further comprises a plurality of third line groups and a plurality of fourth line groups arranged in a same layer as the first line groups, wherein one of the third line groups and one of the fourth line groups are disposed between every two adjacent ones of the first line groups, each of the third line groups and the fourth line groups comprises at least two gate lines, every adjacent pair of the gate lines in the third line groups exhibit a voltage difference, and every adjacent pair of the gate lines in the fourth line groups exhibit a voltage difference, wherein a voltage on at least one gate line in the third line group is different from a voltage on the gate line in the first line group, and in the first line group and the third line group arranged adjacently, the gate line in the third line group close to the first line group has a voltage difference from the gate line in the first line group close to the third line group [Chen FIGs 1-2 & 8 - ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.];
a voltage on at least one gate line in the fourth line group is different from the voltage on the gate line in the first line group, and in the first line group and the fourth line group arranged adjacently, the gate line in the fourth line group close to the first line group has a voltage difference from the gate line in the first line group close to the fourth line group; and in the third line group and the fourth line group arranged adjacently, the gate line in the third line group close to the fourth line group has a voltage difference from the gate line in the fourth line group close to the third line group [Chen FIGs 1-2 & 8 - ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 16: Chen teaches the electronic device according to claim 15, wherein each of the first line groups comprises a first gate line and a second gate line arranged adjacently; each of the third line groups comprises a fifth gate line and a first gate line, and the fifth gate line and the second gate line exhibit a voltage difference; in the first line group and the third line group arranged adjacently, the fifth gate line is close to the first line group; each of the fourth line groups comprises a sixth gate line and the second gate line arranged adjacently, the sixth gate line and the first gate line exhibit a voltage difference, and in the first line group and the fourth line group arranged adjacently, the sixth gate line is close to the first line group [Chen FIGs 1-2 & 8 - ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 17: Chen teaches the electronic device according to claim 16, wherein a voltage on the fifth gate line is equal to a voltage on the sixth gate line [Chen FIGs 1-2 & 8 - ¶22-23 & 28-31- The device is physically capable of achieving equal or different voltages depending on the signals F1/F2 provided to testing pads D1, D2 and D3…. A functional state (equal voltage) that does not required a different physical structure does not provide a structural distinction.].
Claim 18: Chen teaches the electronic device according to claim 11, wherein the display panel further comprises a second non-display area located on another side of the display area; the second non-display area is arranged opposite to the first non-display area and provided with the first line groups and the second line groups; the first line groups and the second line groups in the first non-display area are electrically connected to odd-numbered ones of the gate scan lines; and the first line groups and the second line groups in the second non-display area are electrically connected to even-numbered ones of the gate scan lines [Chen FIG. 1 & ¶21: peripheral device 120 surrounds the display area 110. Fig. 8 shows lines 40 and 50 on different sides of the display area.].
Claim 19: Chen teaches the electronic device according to claim 11, wherein the display panel further comprises a second non-display area located on another side of the display area; the second non-display area is arranged opposite to the first non-display area and provided with the first line groups and the second line groups; the first line groups in the first non-display area are symmetrically arranged with the first line groups in the second non-display area; and the second line groups in the first non-display area are symmetrically arranged with the second line groups in the second non-display area [Chen FIG. 1: depicts symmetrical peripheral non display areas on opposite sides of the display area].
Claim 20: Chen teaches the electronic device according to claim 11, wherein the first line groups or the second line groups are arranged in a same layer as the gate scan lines [Chen ¶22: first sub-signal lines S11 are formed on the first metal layer M1, where M1 is the standard layer for gate lines GA].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/28/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Chen - [0021] Please refer to FIG. 1, which shows a display panel 100 according to the first embodiment of the present invention. As shown in FIG. 1, the display panel comprises a first substrate 20, a plurality of display units 90, a plurality of first signal lines 40, a plurality of pixel control lines CA and testing lines T1 and T2. Each display unit 90 comprises a plurality of pixel units 30. The first substrate 20 has a display area 110 and a peripheral area 120. The peripheral device 120 surrounds the display area 110. The display area 110 is a part of the display panel 100 for displaying images. The peripheral device 120 is the part of the display panel 100 other than the display area 110 and is the area inside the frame of the display panel 100 for disposing circuitries electrically connected to the plurality of pixel units 30. The plurality of pixel units 30 are arranged on the first substrate 20 of the display area 110 in an array or a matrix structure. The pixel control lines CA comprise a plurality of data lines DA and a plurality of gate lines GA configured in the display area 110. The pixel units 30 are electrically connected to the pixel control lines CA. Each pixel unit 30 can be a red, green or blue sub-pixel, but is not limit to these three primary colors. Each pixel unit 30 can also be a cyanine, yellow, magenta or white sub-pixel, for example. Besides, the sub-pixels in the same row or column can be sub-pixels of the same color, and are electrically connected to the same gate line or data line. The sub-pixels in the same row or column are electrically connected to the same sub-signal line. And three sub-pixels marked with R, G and B can form a display unit.
Prosecution Insights